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[PATCH 0/8] Initial LG G Watch R support

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<20210911232707.259615-1-luca@z3ntu.xyz>
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Add support for more msm8226 hardware and the LG G Watch R smartwatch which
is based on apq8026.

Luca Weiss (8):
  pinctrl: qcom: msm8226: fill in more functions
  dt-bindings: mmc: sdhci-msm: Add compatible string for msm8226
  dt-bindings: firmware: scm: Add compatible for msm8226
  ARM: dts: qcom: msm8226: Add more SoC bits
  ARM: dts: qcom: Add pm8226 PMIC
  dt-bindings: vendor-prefixes: add LG Electronics
  dt-bindings: arm: qcom: Document APQ8026 SoC binding
  ARM: dts: qcom: Add support for LG G Watch R

 .../devicetree/bindings/arm/qcom.yaml         |   6 +
 .../devicetree/bindings/firmware/qcom,scm.txt |   1 +
 .../devicetree/bindings/mmc/sdhci-msm.txt     |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 arch/arm/boot/dts/Makefile                    |   1 +
 arch/arm/boot/dts/qcom-apq8026-lge-lenok.dts  | 237 ++++++++++++++++
 arch/arm/boot/dts/qcom-msm8226.dtsi           | 263 +++++++++++++++++-
 arch/arm/boot/dts/qcom-pm8226.dtsi            |  27 ++
 drivers/pinctrl/qcom/pinctrl-msm8226.c        |  74 +++--
 9 files changed, 582 insertions(+), 30 deletions(-)
 create mode 100644 arch/arm/boot/dts/qcom-apq8026-lge-lenok.dts
 create mode 100644 arch/arm/boot/dts/qcom-pm8226.dtsi

-- 
2.33.0

[PATCH 1/8] pinctrl: qcom: msm8226: fill in more functions

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Message ID
<20210911232707.259615-2-luca@z3ntu.xyz>
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<20210911232707.259615-1-luca@z3ntu.xyz> (view parent)
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Patch: +52 -22
Add the functions for QUP4 (spi, uart, uim & i2c), sdc3 and audio_pcm as
derived from the downstream gpiomux configuration.

Also sort the functions alphabetically, while we're at it.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
 drivers/pinctrl/qcom/pinctrl-msm8226.c | 74 ++++++++++++++++++--------
 1 file changed, 52 insertions(+), 22 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c
index 98779e62e951..fca0645e8008 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8226.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c
@@ -338,26 +338,32 @@ static const unsigned int sdc2_data_pins[] = { 122 };
 * the pingroup table below.
 */
enum msm8226_functions {
	MSM_MUX_gpio,
	MSM_MUX_cci_i2c0,
	MSM_MUX_audio_pcm,
	MSM_MUX_blsp_i2c1,
	MSM_MUX_blsp_i2c2,
	MSM_MUX_blsp_i2c3,
	MSM_MUX_blsp_i2c4,
	MSM_MUX_blsp_i2c5,
	MSM_MUX_blsp_spi1,
	MSM_MUX_blsp_spi2,
	MSM_MUX_blsp_spi3,
	MSM_MUX_blsp_spi4,
	MSM_MUX_blsp_spi5,
	MSM_MUX_blsp_uart1,
	MSM_MUX_blsp_uart2,
	MSM_MUX_blsp_uart3,
	MSM_MUX_blsp_uart4,
	MSM_MUX_blsp_uart5,
	MSM_MUX_blsp_uim1,
	MSM_MUX_blsp_uim2,
	MSM_MUX_blsp_uim3,
	MSM_MUX_blsp_uim4,
	MSM_MUX_blsp_uim5,
	MSM_MUX_cam_mclk0,
	MSM_MUX_cam_mclk1,
	MSM_MUX_cci_i2c0,
	MSM_MUX_gpio,
	MSM_MUX_sdc3,
	MSM_MUX_wlan,
	MSM_MUX_NA,
};
@@ -382,6 +388,10 @@ static const char * const gpio_groups[] = {
	"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
};

static const char * const audio_pcm_groups[] = {
	"gpio63", "gpio64", "gpio65", "gpio66"
};

static const char * const blsp_uart1_groups[] = {
	"gpio0", "gpio1", "gpio2", "gpio3"
};
@@ -412,6 +422,16 @@ static const char * const blsp_spi3_groups[] = {
	"gpio8", "gpio9", "gpio10", "gpio11"
};

static const char * const blsp_uart4_groups[] = {
	"gpio12", "gpio13", "gpio14", "gpio15"
};

static const char * const blsp_uim4_groups[] = { "gpio12", "gpio13" };
static const char * const blsp_i2c4_groups[] = { "gpio14", "gpio15" };
static const char * const blsp_spi4_groups[] = {
	"gpio12", "gpio13", "gpio14", "gpio15"
};

static const char * const blsp_uart5_groups[] = {
	"gpio16", "gpio17", "gpio18", "gpio19"
};
@@ -427,31 +447,41 @@ static const char * const cci_i2c0_groups[] = { "gpio29", "gpio30" };
static const char * const cam_mclk0_groups[] = { "gpio26" };
static const char * const cam_mclk1_groups[] = { "gpio27" };

static const char * const sdc3_groups[] = {
	"gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"
};

static const char * const wlan_groups[] = {
	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44"
};

static const struct msm_function msm8226_functions[] = {
	FUNCTION(gpio),
	FUNCTION(cci_i2c0),
	FUNCTION(blsp_uim1),
	FUNCTION(blsp_uim2),
	FUNCTION(blsp_uim3),
	FUNCTION(blsp_uim5),
	FUNCTION(audio_pcm),
	FUNCTION(blsp_i2c1),
	FUNCTION(blsp_i2c2),
	FUNCTION(blsp_i2c3),
	FUNCTION(blsp_i2c4),
	FUNCTION(blsp_i2c5),
	FUNCTION(blsp_spi1),
	FUNCTION(blsp_spi2),
	FUNCTION(blsp_spi3),
	FUNCTION(blsp_spi4),
	FUNCTION(blsp_spi5),
	FUNCTION(blsp_uart1),
	FUNCTION(blsp_uart2),
	FUNCTION(blsp_uart3),
	FUNCTION(blsp_uart4),
	FUNCTION(blsp_uart5),
	FUNCTION(blsp_uim1),
	FUNCTION(blsp_uim2),
	FUNCTION(blsp_uim3),
	FUNCTION(blsp_uim4),
	FUNCTION(blsp_uim5),
	FUNCTION(cam_mclk0),
	FUNCTION(cam_mclk1),
	FUNCTION(cci_i2c0),
	FUNCTION(gpio),
	FUNCTION(sdc3),
	FUNCTION(wlan),
};

@@ -468,10 +498,10 @@ static const struct msm_pingroup msm8226_groups[] = {
	PINGROUP(9,   blsp_spi3, blsp_uart3, blsp_uim3, NA, NA, NA, NA),
	PINGROUP(10,  blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
	PINGROUP(11,  blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
	PINGROUP(12,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(13,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(14,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(15,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(12,  blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA),
	PINGROUP(13,  blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA),
	PINGROUP(14,  blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA),
	PINGROUP(15,  blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA),
	PINGROUP(16,  blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
	PINGROUP(17,  blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
	PINGROUP(18,  blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
@@ -495,12 +525,12 @@ static const struct msm_pingroup msm8226_groups[] = {
	PINGROUP(36,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(37,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(38,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(39,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(40,  wlan, NA, NA, NA, NA, NA, NA),
	PINGROUP(41,  wlan, NA, NA, NA, NA, NA, NA),
	PINGROUP(42,  wlan, NA, NA, NA, NA, NA, NA),
	PINGROUP(43,  wlan, NA, NA, NA, NA, NA, NA),
	PINGROUP(44,  wlan, NA, NA, NA, NA, NA, NA),
	PINGROUP(39,  NA, sdc3, NA, NA, NA, NA, NA),
	PINGROUP(40,  wlan, sdc3, NA, NA, NA, NA, NA),
	PINGROUP(41,  wlan, sdc3, NA, NA, NA, NA, NA),
	PINGROUP(42,  wlan, sdc3, NA, NA, NA, NA, NA),
	PINGROUP(43,  wlan, sdc3, NA, NA, NA, NA, NA),
	PINGROUP(44,  wlan, sdc3, NA, NA, NA, NA, NA),
	PINGROUP(45,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(46,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(47,  NA, NA, NA, NA, NA, NA, NA),
@@ -519,10 +549,10 @@ static const struct msm_pingroup msm8226_groups[] = {
	PINGROUP(60,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(61,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(62,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(63,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(64,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(65,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(66,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(63,  audio_pcm, NA, NA, NA, NA, NA, NA),
	PINGROUP(64,  audio_pcm, NA, NA, NA, NA, NA, NA),
	PINGROUP(65,  audio_pcm, NA, NA, NA, NA, NA, NA),
	PINGROUP(66,  audio_pcm, NA, NA, NA, NA, NA, NA),
	PINGROUP(67,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(68,  NA, NA, NA, NA, NA, NA, NA),
	PINGROUP(69,  NA, NA, NA, NA, NA, NA, NA),
-- 
2.33.0

[PATCH 2/8] dt-bindings: mmc: sdhci-msm: Add compatible string for msm8226

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<20210911232707.259615-3-luca@z3ntu.xyz>
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Patch: +1 -0
Add msm8226 SoC specific compatible strings for qcom-sdhci controller.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
 Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
index 365c3fc122ea..50841e2843fc 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
@@ -13,6 +13,7 @@ Required properties:
		string is added to support this change - "qcom,sdhci-msm-v5".
	full compatible strings with SoC and version:
		"qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
		"qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"
		"qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
		"qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
		"qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
-- 
2.33.0

[PATCH 3/8] dt-bindings: firmware: scm: Add compatible for msm8226

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Message ID
<20210911232707.259615-4-luca@z3ntu.xyz>
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Patch: +1 -0
Add devicetree compatible for SCM present in msm8226 platform.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
 Documentation/devicetree/bindings/firmware/qcom,scm.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.txt b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
index a7333ad938d2..5a90e84b8dcf 100644
--- a/Documentation/devicetree/bindings/firmware/qcom,scm.txt
+++ b/Documentation/devicetree/bindings/firmware/qcom,scm.txt
@@ -13,6 +13,7 @@ Required properties:
 * "qcom,scm-ipq806x"
 * "qcom,scm-ipq8074"
 * "qcom,scm-mdm9607"
 * "qcom,scm-msm8226"
 * "qcom,scm-msm8660"
 * "qcom,scm-msm8916"
 * "qcom,scm-msm8960"
-- 
2.33.0

[PATCH 4/8] ARM: dts: qcom: msm8226: Add more SoC bits

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<20210911232707.259615-5-luca@z3ntu.xyz>
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Patch: +255 -8
Add nodes for sdhc, uart4, i2c, scm, smem, rpm-requests including
dependencies.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
 arch/arm/boot/dts/qcom-msm8226.dtsi | 263 +++++++++++++++++++++++++++-
 1 file changed, 255 insertions(+), 8 deletions(-)

diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi
index 2de69d56870d..72efd565c6ae 100644
--- a/arch/arm/boot/dts/qcom-msm8226.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
@@ -7,6 +7,7 @@

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8974.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	#address-cells = <1>;
@@ -20,6 +21,20 @@ memory@0 {
		reg = <0x0 0x0>;
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <1>;
@@ -34,6 +49,136 @@ intc: interrupt-controller@f9000000 {
			#interrupt-cells = <3>;
		};

		apcs: syscon@f9011000 {
			compatible = "syscon";
			reg = <0xf9011000 0x1000>;
		};

		sdhc_1: sdhci@f9824900 {
			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
				 <&gcc GCC_SDCC1_AHB_CLK>,
				 <&xo_board>;
			clock-names = "core", "iface", "xo";
			status = "disabled";
		};

		sdhc_2: sdhci@f98a4900 {
			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
				 <&gcc GCC_SDCC2_AHB_CLK>,
				 <&xo_board>;
			clock-names = "core", "iface", "xo";
			status = "disabled";
		};

		sdhc_3: sdhci@f9864900 {
			compatible = "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4";
			reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC3_APPS_CLK>,
				 <&gcc GCC_SDCC3_AHB_CLK>,
				 <&xo_board>;
			clock-names = "core", "iface", "xo";
			status = "disabled";
		};

		blsp1_uart3: serial@f991f000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991f000 0x1000>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_uart4: serial@f9920000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf9920000 0x1000>;
			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		blsp1_i2c1: i2c@f9923000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9923000 0x1000>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c1_pins>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c2: i2c@f9924000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9924000 0x1000>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c2_pins>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c3: i2c@f9925000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9925000 0x1000>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c3_pins>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c4: i2c@f9926000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9926000 0x1000>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c4_pins>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		blsp1_i2c5: i2c@f9927000 {
			status = "disabled";
			compatible = "qcom,i2c-qup-v2.1.1";
			reg = <0xf9927000 0x1000>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			pinctrl-names = "default";
			pinctrl-0 = <&blsp1_i2c5_pins>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

		gcc: clock-controller@fc400000 {
			compatible = "qcom,gcc-msm8226";
			reg = <0xfc400000 0x4000>;
@@ -51,15 +196,41 @@ tlmm: pinctrl@fd510000 {
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
		};

		blsp1_uart3: serial@f991f000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf991f000 0x1000>;
			interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
			blsp1_i2c1_pins: blsp1-i2c1 {
				pins = "gpio2", "gpio3";
				function = "blsp_i2c1";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c2_pins: blsp1-i2c2 {
				pins = "gpio6", "gpio7";
				function = "blsp_i2c2";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c3_pins: blsp1-i2c3 {
				pins = "gpio10", "gpio11";
				function = "blsp_i2c3";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c4_pins: blsp1-i2c4 {
				pins = "gpio14", "gpio15";
				function = "blsp_i2c4";
				drive-strength = <2>;
				bias-disable;
			};

			blsp1_i2c5_pins: blsp1-i2c5 {
				pins = "gpio18", "gpio19";
				function = "blsp_i2c5";
				drive-strength = <2>;
				bias-disable;
			};
		};

		restart@fc4ab000 {
@@ -67,6 +238,22 @@ restart@fc4ab000 {
			reg = <0xfc4ab000 0x4>;
		};

		spmi_bus: spmi@fc4cf000 {
			compatible = "qcom,spmi-pmic-arb";
			reg-names = "core", "intr", "cnfg";
			reg = <0xfc4cf000 0x1000>,
			      <0xfc4cb000 0x1000>,
			      <0xfc4ca000 0x1000>;
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		rng@f9bff000 {
			compatible = "qcom,prng";
			reg = <0xf9bff000 0x200>;
@@ -131,6 +318,66 @@ frame@f9028000 {
				status = "disabled";
			};
		};

		rpm_msg_ram: memory@fc428000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0xfc428000 0x4000>;
		};

		tcsr_mutex_block: syscon@fd484000 {
			compatible = "syscon";
			reg = <0xfd484000 0x2000>;
		};
	};

	firmware {
		scm {
			compatible = "qcom,scm-msm8226", "qcom,scm";
			clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
			clock-names = "core", "bus", "iface";
		};
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x80>;

		#hwlock-cells = <1>;
	};

	reserved-memory {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		smem_region: smem@3000000 {
			reg = <0x3000000 0x100000>;
			no-map;
		};
	};

	smd {
		compatible = "qcom,smd";

		rpm {
			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;

			rpm_requests: rpm-requests {
				compatible = "qcom,rpm-msm8226";
				qcom,smd-channels = "rpm_requests";
			};
		};
	};

	smem {
		compatible = "qcom,smem";

		memory-region = <&smem_region>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;

		hwlocks = <&tcsr_mutex 3>;
	};

	timer {
-- 
2.33.0

[PATCH 5/8] ARM: dts: qcom: Add pm8226 PMIC

Details
Message ID
<20210911232707.259615-6-luca@z3ntu.xyz>
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Patch: +27 -0
The pm8226 is used with Qualcomm platforms, like msm8226.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
 arch/arm/boot/dts/qcom-pm8226.dtsi | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-pm8226.dtsi

diff --git a/arch/arm/boot/dts/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom-pm8226.dtsi
new file mode 100644
index 000000000000..dddb5150dfd7
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-pm8226.dtsi
@@ -0,0 +1,27 @@
// SPDX-License-Identifier: BSD-3-Clause
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>

&spmi_bus {
	pm8226_0: pm8226@0 {
		compatible = "qcom,pm8226", "qcom,spmi-pmic";
		reg = <0x0 SPMI_USID>;
		#address-cells = <1>;
		#size-cells = <0>;

		pwrkey@800 {
			compatible = "qcom,pm8941-pwrkey";
			reg = <0x800>;
			interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>;
			debounce = <15625>;
			bias-pull-up;
		};
	};

	pm8226_1: pm8226@1 {
		compatible = "qcom,pm8226", "qcom,spmi-pmic";
		reg = <0x1 SPMI_USID>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
};
-- 
2.33.0

[PATCH 6/8] dt-bindings: vendor-prefixes: add LG Electronics

Details
Message ID
<20210911232707.259615-7-luca@z3ntu.xyz>
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Patch: +2 -0
LG Electronics is a part of the LG Corporation and produces, amongst
other things, consumer electronics such as phones and smartwatches.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index a867f7102c35..b99af98bf5de 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -635,6 +635,8 @@ patternProperties:
    description: Lenovo Group Ltd.
  "^lg,.*":
    description: LG Corporation
  "^lge,.*":
    description: LG Electronics Inc.
  "^lgphilips,.*":
    description: LG Display
  "^libretech,.*":
-- 
2.33.0

[PATCH 7/8] dt-bindings: arm: qcom: Document APQ8026 SoC binding

Details
Message ID
<20210911232707.259615-8-luca@z3ntu.xyz>
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Patch: +6 -0
Document the APQ8026 (based on MSM8226) SoC device-tree binding and the
LG G Watch R.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
 Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
index 880ddafc634e..da44688133af 100644
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
@@ -25,6 +25,7 @@ description: |
  The 'SoC' element must be one of the following strings:

        apq8016
        apq8026
        apq8074
        apq8084
        apq8096
@@ -92,6 +93,11 @@ properties:
              - qcom,apq8016-sbc
          - const: qcom,apq8016

      - items:
          - enum:
              - lge,lenok
          - const: qcom,apq8026

      - items:
          - enum:
              - qcom,apq8064-cm-qs600
-- 
2.33.0

[PATCH 8/8] ARM: dts: qcom: Add support for LG G Watch R

Details
Message ID
<20210911232707.259615-9-luca@z3ntu.xyz>
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Patch: +238 -0
Add a device tree for the LG G Watch R smartwatch, manufactured by LG
Electronics and based on the msm8226 platform (apq8026).

Currently UART, internal storage, power button and touchscreen are
supported.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
---
 arch/arm/boot/dts/Makefile                   |   1 +
 arch/arm/boot/dts/qcom-apq8026-lge-lenok.dts | 237 +++++++++++++++++++
 2 files changed, 238 insertions(+)
 create mode 100644 arch/arm/boot/dts/qcom-apq8026-lge-lenok.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e0934180724..8cb859728bd9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -939,6 +939,7 @@ dtb-$(CONFIG_ARCH_OXNAS) += \
	ox810se-wd-mbwe.dtb \
	ox820-cloudengines-pogoplug-series-3.dtb
dtb-$(CONFIG_ARCH_QCOM) += \
	qcom-apq8026-lge-lenok.dtb \
	qcom-apq8060-dragonboard.dtb \
	qcom-apq8064-cm-qs600.dtb \
	qcom-apq8064-ifc6410.dtb \
diff --git a/arch/arm/boot/dts/qcom-apq8026-lge-lenok.dts b/arch/arm/boot/dts/qcom-apq8026-lge-lenok.dts
new file mode 100644
index 000000000000..02c8dfb0988a
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8026-lge-lenok.dts
@@ -0,0 +1,237 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
 * Copyright (c) 2021, Luca Weiss <luca@z3ntu.xyz>
 */

/dts-v1/;

#include "qcom-msm8226.dtsi"
#include "qcom-pm8226.dtsi"

/ {
	model = "LG G Watch R";
	compatible = "lge,lenok", "qcom,apq8026";
	qcom,board-id = <132 0x0a>;
	qcom,msm-id = <199 0x20000>;

	aliases {
		serial0 = &blsp1_uart3;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&blsp1_i2c5 {
	status = "okay";
	clock-frequency = <384000>;

	touchscreen@20 {
		compatible = "syna,rmi4-i2c";
		reg = <0x20>;

		interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>;
		vdd-supply = <&pm8226_l15>;
		vio-supply = <&pm8226_l22>;

		pinctrl-names = "default";
		pinctrl-0 = <&touch_pins>;

		#address-cells = <1>;
		#size-cells = <0>;

		rmi4-f01@1 {
			reg = <0x1>;
			syna,nosleep-mode = <1>;
		};

		rmi4-f12@12 {
			reg = <0x12>;
			syna,sensor-type = <1>;
		};
	};
};

&blsp1_uart3 {
	status = "okay";
};

&sdhc_1 {
	status = "okay";

	vmmc-supply = <&pm8226_l17>;
	vqmmc-supply = <&pm8226_l6>;

	bus-width = <8>;
	non-removable;

	pinctrl-names = "default";
	pinctrl-0 = <&sdhc1_pin_a>;
};

&rpm_requests {
	pm8226-regulators {
		compatible = "qcom,rpm-pm8226-regulators";

		pm8226_s1: s1 {
			regulator-min-microvolt = <500000>;
			regulator-max-microvolt = <1275000>;
		};
		pm8226_s3: s3 {
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1350000>;
		};
		pm8226_s4: s4 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <2200000>;
		};
		pm8226_s5: s5 {
			regulator-min-microvolt = <1150000>;
			regulator-max-microvolt = <1150000>;
		};

		pm8226_l1: l1 {
			regulator-min-microvolt = <1225000>;
			regulator-max-microvolt = <1225000>;
		};
		pm8226_l2: l2 {
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1200000>;
		};
		pm8226_l3: l3 {
			regulator-min-microvolt = <750000>;
			regulator-max-microvolt = <1337500>;
		};
		pm8226_l4: l4 {
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1200000>;
		};
		pm8226_l5: l5 {
			regulator-min-microvolt = <1200000>;
			regulator-max-microvolt = <1200000>;
		};
		pm8226_l6: l6 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};
		pm8226_l7: l7 {
			regulator-min-microvolt = <1850000>;
			regulator-max-microvolt = <1850000>;
		};
		pm8226_l8: l8 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};
		pm8226_l9: l9 {
			regulator-min-microvolt = <2050000>;
			regulator-max-microvolt = <2050000>;
		};
		pm8226_l10: l10 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};
		pm8226_l12: l12 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};
		pm8226_l14: l14 {
			regulator-min-microvolt = <2750000>;
			regulator-max-microvolt = <2750000>;
		};
		pm8226_l15: l15 {
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
		};
		pm8226_l16: l16 {
			regulator-min-microvolt = <3000000>;
			regulator-max-microvolt = <3350000>;
		};
		pm8226_l17: l17 {
			regulator-min-microvolt = <2950000>;
			regulator-max-microvolt = <2950000>;
		};
		pm8226_l18: l18 {
			regulator-min-microvolt = <3000000>;
			regulator-max-microvolt = <3300000>;
		};
		pm8226_l19: l19 {
			regulator-min-microvolt = <3000000>;
			regulator-max-microvolt = <3000000>;
		};
		pm8226_l20: l20 {
			regulator-min-microvolt = <3075000>;
			regulator-max-microvolt = <3075000>;
		};
		pm8226_l21: l21 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <2950000>;
		};
		pm8226_l22: l22 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};
		pm8226_l23: l23 {
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <2950000>;
		};
		pm8226_l24: l24 {
			regulator-min-microvolt = <1300000>;
			regulator-max-microvolt = <1350000>;
		};
		pm8226_l25: l25 {
			regulator-min-microvolt = <1775000>;
			regulator-max-microvolt = <2125000>;
		};
		pm8226_l26: l26 {
			regulator-min-microvolt = <1225000>;
			regulator-max-microvolt = <1225000>;
		};
		pm8226_l27: l27 {
			regulator-min-microvolt = <2050000>;
			regulator-max-microvolt = <2050000>;
		};
		pm8226_l28: l28 {
			regulator-min-microvolt = <2700000>;
			regulator-max-microvolt = <3000000>;
		};

		pm8226_lvs1: lvs1 {};
	};
};

&tlmm {
	sdhc1_pin_a: sdhc1-pin-active {
		clk {
			pins = "sdc1_clk";
			drive-strength = <10>;
			bias-disable;
		};

		cmd-data {
			pins = "sdc1_cmd", "sdc1_data";
			drive-strength = <10>;
			bias-pull-up;
		};
	};

	touch_pins: touch {
		irq {
			pins = "gpio17";
			function = "gpio";

			drive-strength = <8>;
			bias-pull-down;
			input-enable;
		};

		reset {
			pins = "gpio16";
			function = "gpio";

			drive-strength = <8>;
			bias-disable;
			output-high;
		};
	};
};
-- 
2.33.0

Re: [PATCH 6/8] dt-bindings: vendor-prefixes: add LG Electronics

Details
Message ID
<9942f964-442e-e782-3926-6d7d1123418a@canonical.com>
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<20210911232707.259615-7-luca@z3ntu.xyz> (view parent)
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On 12/09/2021 01:27, Luca Weiss wrote:
> LG Electronics is a part of the LG Corporation and produces, amongst
> other things, consumer electronics such as phones and smartwatches.

Hi,

Thanks for the patches.

I think "lge" it's the same prefix as "lg". There is no sense in having
multiple vendor prefixes just because company splits inside business
units or subsidiaries. The same as with other conglomerates, e.g.
Samsung - if we wanted to be specific, there will be 4-5 Samsung
vendors... Not mentioning that company organisation is not always
disclosed and can change.

We already have lg for several components, also made by LG Electronics.
What about these?

There is only one device with "lge", added back in 2016 without adding
vendor prefix. I would propose to fix that one, instead of keeping
duplicated "lg".

Best regards,
Krzysztof

Re: [PATCH 1/8] pinctrl: qcom: msm8226: fill in more functions

Details
Message ID
<YT+OLEldZ0ZGGWvV@builder.lan>
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On Sat 11 Sep 18:26 CDT 2021, Luca Weiss wrote:

> Add the functions for QUP4 (spi, uart, uim & i2c), sdc3 and audio_pcm as
> derived from the downstream gpiomux configuration.
> 
> Also sort the functions alphabetically, while we're at it.
> 
> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Regards,
Bjorn

> ---
>  drivers/pinctrl/qcom/pinctrl-msm8226.c | 74 ++++++++++++++++++--------
>  1 file changed, 52 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/pinctrl/qcom/pinctrl-msm8226.c b/drivers/pinctrl/qcom/pinctrl-msm8226.c
> index 98779e62e951..fca0645e8008 100644
> --- a/drivers/pinctrl/qcom/pinctrl-msm8226.c
> +++ b/drivers/pinctrl/qcom/pinctrl-msm8226.c
> @@ -338,26 +338,32 @@ static const unsigned int sdc2_data_pins[] = { 122 };
>   * the pingroup table below.
>   */
>  enum msm8226_functions {
> -	MSM_MUX_gpio,
> -	MSM_MUX_cci_i2c0,
> +	MSM_MUX_audio_pcm,
>  	MSM_MUX_blsp_i2c1,
>  	MSM_MUX_blsp_i2c2,
>  	MSM_MUX_blsp_i2c3,
> +	MSM_MUX_blsp_i2c4,
>  	MSM_MUX_blsp_i2c5,
>  	MSM_MUX_blsp_spi1,
>  	MSM_MUX_blsp_spi2,
>  	MSM_MUX_blsp_spi3,
> +	MSM_MUX_blsp_spi4,
>  	MSM_MUX_blsp_spi5,
>  	MSM_MUX_blsp_uart1,
>  	MSM_MUX_blsp_uart2,
>  	MSM_MUX_blsp_uart3,
> +	MSM_MUX_blsp_uart4,
>  	MSM_MUX_blsp_uart5,
>  	MSM_MUX_blsp_uim1,
>  	MSM_MUX_blsp_uim2,
>  	MSM_MUX_blsp_uim3,
> +	MSM_MUX_blsp_uim4,
>  	MSM_MUX_blsp_uim5,
>  	MSM_MUX_cam_mclk0,
>  	MSM_MUX_cam_mclk1,
> +	MSM_MUX_cci_i2c0,
> +	MSM_MUX_gpio,
> +	MSM_MUX_sdc3,
>  	MSM_MUX_wlan,
>  	MSM_MUX_NA,
>  };
> @@ -382,6 +388,10 @@ static const char * const gpio_groups[] = {
>  	"gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
>  };
>  
> +static const char * const audio_pcm_groups[] = {
> +	"gpio63", "gpio64", "gpio65", "gpio66"
> +};
> +
>  static const char * const blsp_uart1_groups[] = {
>  	"gpio0", "gpio1", "gpio2", "gpio3"
>  };
> @@ -412,6 +422,16 @@ static const char * const blsp_spi3_groups[] = {
>  	"gpio8", "gpio9", "gpio10", "gpio11"
>  };
>  
> +static const char * const blsp_uart4_groups[] = {
> +	"gpio12", "gpio13", "gpio14", "gpio15"
> +};
> +
> +static const char * const blsp_uim4_groups[] = { "gpio12", "gpio13" };
> +static const char * const blsp_i2c4_groups[] = { "gpio14", "gpio15" };
> +static const char * const blsp_spi4_groups[] = {
> +	"gpio12", "gpio13", "gpio14", "gpio15"
> +};
> +
>  static const char * const blsp_uart5_groups[] = {
>  	"gpio16", "gpio17", "gpio18", "gpio19"
>  };
> @@ -427,31 +447,41 @@ static const char * const cci_i2c0_groups[] = { "gpio29", "gpio30" };
>  static const char * const cam_mclk0_groups[] = { "gpio26" };
>  static const char * const cam_mclk1_groups[] = { "gpio27" };
>  
> +static const char * const sdc3_groups[] = {
> +	"gpio39", "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"
> +};
> +
>  static const char * const wlan_groups[] = {
>  	"gpio40", "gpio41", "gpio42", "gpio43", "gpio44"
>  };
>  
>  static const struct msm_function msm8226_functions[] = {
> -	FUNCTION(gpio),
> -	FUNCTION(cci_i2c0),
> -	FUNCTION(blsp_uim1),
> -	FUNCTION(blsp_uim2),
> -	FUNCTION(blsp_uim3),
> -	FUNCTION(blsp_uim5),
> +	FUNCTION(audio_pcm),
>  	FUNCTION(blsp_i2c1),
>  	FUNCTION(blsp_i2c2),
>  	FUNCTION(blsp_i2c3),
> +	FUNCTION(blsp_i2c4),
>  	FUNCTION(blsp_i2c5),
>  	FUNCTION(blsp_spi1),
>  	FUNCTION(blsp_spi2),
>  	FUNCTION(blsp_spi3),
> +	FUNCTION(blsp_spi4),
>  	FUNCTION(blsp_spi5),
>  	FUNCTION(blsp_uart1),
>  	FUNCTION(blsp_uart2),
>  	FUNCTION(blsp_uart3),
> +	FUNCTION(blsp_uart4),
>  	FUNCTION(blsp_uart5),
> +	FUNCTION(blsp_uim1),
> +	FUNCTION(blsp_uim2),
> +	FUNCTION(blsp_uim3),
> +	FUNCTION(blsp_uim4),
> +	FUNCTION(blsp_uim5),
>  	FUNCTION(cam_mclk0),
>  	FUNCTION(cam_mclk1),
> +	FUNCTION(cci_i2c0),
> +	FUNCTION(gpio),
> +	FUNCTION(sdc3),
>  	FUNCTION(wlan),
>  };
>  
> @@ -468,10 +498,10 @@ static const struct msm_pingroup msm8226_groups[] = {
>  	PINGROUP(9,   blsp_spi3, blsp_uart3, blsp_uim3, NA, NA, NA, NA),
>  	PINGROUP(10,  blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
>  	PINGROUP(11,  blsp_spi3, blsp_uart3, blsp_i2c3, NA, NA, NA, NA),
> -	PINGROUP(12,  NA, NA, NA, NA, NA, NA, NA),
> -	PINGROUP(13,  NA, NA, NA, NA, NA, NA, NA),
> -	PINGROUP(14,  NA, NA, NA, NA, NA, NA, NA),
> -	PINGROUP(15,  NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(12,  blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA),
> +	PINGROUP(13,  blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA, NA),
> +	PINGROUP(14,  blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA),
> +	PINGROUP(15,  blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA, NA),
>  	PINGROUP(16,  blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
>  	PINGROUP(17,  blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA, NA),
>  	PINGROUP(18,  blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA, NA),
> @@ -495,12 +525,12 @@ static const struct msm_pingroup msm8226_groups[] = {
>  	PINGROUP(36,  NA, NA, NA, NA, NA, NA, NA),
>  	PINGROUP(37,  NA, NA, NA, NA, NA, NA, NA),
>  	PINGROUP(38,  NA, NA, NA, NA, NA, NA, NA),
> -	PINGROUP(39,  NA, NA, NA, NA, NA, NA, NA),
> -	PINGROUP(40,  wlan, NA, NA, NA, NA, NA, NA),
> -	PINGROUP(41,  wlan, NA, NA, NA, NA, NA, NA),
> -	PINGROUP(42,  wlan, NA, NA, NA, NA, NA, NA),
> -	PINGROUP(43,  wlan, NA, NA, NA, NA, NA, NA),
> -	PINGROUP(44,  wlan, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(39,  NA, sdc3, NA, NA, NA, NA, NA),
> +	PINGROUP(40,  wlan, sdc3, NA, NA, NA, NA, NA),
> +	PINGROUP(41,  wlan, sdc3, NA, NA, NA, NA, NA),
> +	PINGROUP(42,  wlan, sdc3, NA, NA, NA, NA, NA),
> +	PINGROUP(43,  wlan, sdc3, NA, NA, NA, NA, NA),
> +	PINGROUP(44,  wlan, sdc3, NA, NA, NA, NA, NA),
>  	PINGROUP(45,  NA, NA, NA, NA, NA, NA, NA),
>  	PINGROUP(46,  NA, NA, NA, NA, NA, NA, NA),
>  	PINGROUP(47,  NA, NA, NA, NA, NA, NA, NA),
> @@ -519,10 +549,10 @@ static const struct msm_pingroup msm8226_groups[] = {
>  	PINGROUP(60,  NA, NA, NA, NA, NA, NA, NA),
>  	PINGROUP(61,  NA, NA, NA, NA, NA, NA, NA),
>  	PINGROUP(62,  NA, NA, NA, NA, NA, NA, NA),
> -	PINGROUP(63,  NA, NA, NA, NA, NA, NA, NA),
> -	PINGROUP(64,  NA, NA, NA, NA, NA, NA, NA),
> -	PINGROUP(65,  NA, NA, NA, NA, NA, NA, NA),
> -	PINGROUP(66,  NA, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(63,  audio_pcm, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(64,  audio_pcm, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(65,  audio_pcm, NA, NA, NA, NA, NA, NA),
> +	PINGROUP(66,  audio_pcm, NA, NA, NA, NA, NA, NA),
>  	PINGROUP(67,  NA, NA, NA, NA, NA, NA, NA),
>  	PINGROUP(68,  NA, NA, NA, NA, NA, NA, NA),
>  	PINGROUP(69,  NA, NA, NA, NA, NA, NA, NA),
> -- 
> 2.33.0
> 

Re: [PATCH 6/8] dt-bindings: vendor-prefixes: add LG Electronics

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<5220943.AHGTne7y6d@g550jk>
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<9942f964-442e-e782-3926-6d7d1123418a@canonical.com> (view parent)
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Hi Krzysztof,

On Montag, 13. September 2021 10:49:43 CEST Krzysztof Kozlowski wrote:
> On 12/09/2021 01:27, Luca Weiss wrote:
> > LG Electronics is a part of the LG Corporation and produces, amongst
> > other things, consumer electronics such as phones and smartwatches.
> 
> Hi,
> 
> Thanks for the patches.
> 
> I think "lge" it's the same prefix as "lg". There is no sense in having
> multiple vendor prefixes just because company splits inside business
> units or subsidiaries. The same as with other conglomerates, e.g.
> Samsung - if we wanted to be specific, there will be 4-5 Samsung
> vendors... Not mentioning that company organisation is not always
> disclosed and can change.
> 

I was mostly following qcom-msm8974-lge-nexus5-hammerhead as it's the other LG 
device tree I am aware of so I've picked lge instead of lg. Also worth noting 
that Google uses "LGE" in the Android device tree[1] or in the model name in 
the LG G Watch R kernel sources ("LGE APQ 8026v2 LENOK rev-1.0").

I don't have a strong opinion either way so I'm fine with either.

If we decide to go with "lg" do we want to change the Nexus 5 devicetree 
(hammerhead) also, that one has the lge name in at least compatible and 
filename (I don't know how much of a breaking change that would be considered 
as).

> We already have lg for several components, also made by LG Electronics.
> What about these?
> 
> There is only one device with "lge", added back in 2016 without adding
> vendor prefix. I would propose to fix that one, instead of keeping
> duplicated "lg".
> 
> Best regards,
> Krzysztof

Regards
Luca

[1] https://android.googlesource.com/device/lge/hammerhead/

Re: [PATCH 6/8] dt-bindings: vendor-prefixes: add LG Electronics

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On 13/09/2021 21:14, Luca Weiss wrote:
> Hi Krzysztof,
> 
> On Montag, 13. September 2021 10:49:43 CEST Krzysztof Kozlowski wrote:
>> On 12/09/2021 01:27, Luca Weiss wrote:
>>> LG Electronics is a part of the LG Corporation and produces, amongst
>>> other things, consumer electronics such as phones and smartwatches.
>>
>> Hi,
>>
>> Thanks for the patches.
>>
>> I think "lge" it's the same prefix as "lg". There is no sense in having
>> multiple vendor prefixes just because company splits inside business
>> units or subsidiaries. The same as with other conglomerates, e.g.
>> Samsung - if we wanted to be specific, there will be 4-5 Samsung
>> vendors... Not mentioning that company organisation is not always
>> disclosed and can change.
>>
> 
> I was mostly following qcom-msm8974-lge-nexus5-hammerhead as it's the other LG 
> device tree I am aware of so I've picked lge instead of lg. Also worth noting 
> that Google uses "LGE" in the Android device tree[1] or in the model name in 
> the LG G Watch R kernel sources ("LGE APQ 8026v2 LENOK rev-1.0")

[1] Does not point to kernel tree. Downstream user could be a good
argument to switch to lge, but then I would expect correcting other "lg"
devices which are in fact made by LGE.

> 
> I don't have a strong opinion either way so I'm fine with either.
> 
> If we decide to go with "lg" do we want to change the Nexus 5 devicetree 
> (hammerhead) also, that one has the lge name in at least compatible and 
> filename (I don't know how much of a breaking change that would be considered 
> as).

We would have to add a new one and mark the old compatible as deprecated.

> 
>> We already have lg for several components, also made by LG Electronics.
>> What about these?
>>
>> There is only one device with "lge", added back in 2016 without adding
>> vendor prefix. I would propose to fix that one, instead of keeping
>> duplicated "lg".
>>
>> Best regards,
>> Krzysztof
> 
> Regards
> Luca
> 
> [1] https://android.googlesource.com/device/lge/hammerhead/
> 
> 
> 


Best regards,
Krzysztof

Re: [PATCH 2/8] dt-bindings: mmc: sdhci-msm: Add compatible string for msm8226

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<CAPDyKFr9k2dO8FJf4=ZUKZ6=WpDS2mOJ+BZbtK1m_-OWx_ehmA@mail.gmail.com>
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On Sun, 12 Sept 2021 at 01:28, Luca Weiss <luca@z3ntu.xyz> wrote:
>
> Add msm8226 SoC specific compatible strings for qcom-sdhci controller.
>
> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>

Applied for next, thanks!

Kind regards
Uffe


> ---
>  Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> index 365c3fc122ea..50841e2843fc 100644
> --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt
> @@ -13,6 +13,7 @@ Required properties:
>                 string is added to support this change - "qcom,sdhci-msm-v5".
>         full compatible strings with SoC and version:
>                 "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
> +               "qcom,msm8226-sdhci", "qcom,sdhci-msm-v4"
>                 "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
>                 "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
>                 "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
> --
> 2.33.0
>

Re: [PATCH 1/8] pinctrl: qcom: msm8226: fill in more functions

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<CACRpkda0Jm=JwxpsmU63m94hFsL1Lhuk3mfjgFuXLNJ3RjdUnA@mail.gmail.com>
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On Sun, Sep 12, 2021 at 1:28 AM Luca Weiss <luca@z3ntu.xyz> wrote:

> Add the functions for QUP4 (spi, uart, uim & i2c), sdc3 and audio_pcm as
> derived from the downstream gpiomux configuration.
>
> Also sort the functions alphabetically, while we're at it.
>
> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>

This patch applied to the pinctrl tree for v5.16.

Yours,
Linus Walleij

Re: [PATCH 7/8] dt-bindings: arm: qcom: Document APQ8026 SoC binding

Rob Herring <robh@kernel.org>
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<YUkC1q65RjkwBaAj@robh.at.kernel.org>
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On Sun, Sep 12, 2021 at 01:27:01AM +0200, Luca Weiss wrote:
> Document the APQ8026 (based on MSM8226) SoC device-tree binding and the
> LG G Watch R.

Looks like this was applied, but lg vs. lge needs to be sorted first. 
IMO, we should fix the one instance of 'lge'.

> 
> Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
> ---
>  Documentation/devicetree/bindings/arm/qcom.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
> index 880ddafc634e..da44688133af 100644
> --- a/Documentation/devicetree/bindings/arm/qcom.yaml
> +++ b/Documentation/devicetree/bindings/arm/qcom.yaml
> @@ -25,6 +25,7 @@ description: |
>    The 'SoC' element must be one of the following strings:
>  
>          apq8016
> +        apq8026
>          apq8074
>          apq8084
>          apq8096
> @@ -92,6 +93,11 @@ properties:
>                - qcom,apq8016-sbc
>            - const: qcom,apq8016
>  
> +      - items:
> +          - enum:
> +              - lge,lenok
> +          - const: qcom,apq8026
> +
>        - items:
>            - enum:
>                - qcom,apq8064-cm-qs600
> -- 
> 2.33.0
> 
> 
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