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Cleanup & sort msm8916.dtsi, various minor fixes v1 PROPOSED

Stephan Gerhold
After cleaning up the MSM8916 board device tree files [1], this patch series
focuses on various cleanup and minor fixes within the common msm8916.dtsi:

  1. One more conversion to use labels to configure board DSI ports
     (I missed that in the last patch series)
  2. A few non-critical fixes just to make the device tree more correct
  3. A few style fixes (e.g. replacing spaces with tabs)
  4. Sort nodes in msm8916.dtsi/pm8916.dtsi and the Makefile

This brings MSM8916 close to the conventions used for newer SoCs,
and will make it easier to add new device nodes (e.g. CPR) to it later.

[1]: https://lore.kernel.org/linux-arm-msm/20200720085406.6716-1-stephan@gerhold.net/

Stephan Gerhold (14):
  arm64: dts: qcom: msm8916: Configure DSI port with labels
  arm64: dts: qcom: msm8916: Remove one more thermal trip point unit
    name
  arm64: dts: qcom: pm8916: Remove invalid reg size from wcd_codec
  arm64: dts: qcom: msm8916: Fix MDP/DSI interrupts
  arm64: dts: qcom: msm8916: Use IRQ defines, add IRQ types
  arm64: dts: qcom: msm8916: Drop qcom,tcsr-mutex syscon
  arm64: dts: qcom: msm8916: Minor style fixes
  arm64: dts: qcom: msm8916: Add MSM8916-specific compatibles to SCM/MSS
  arm64: dts: qcom: msm8916: Use more generic node names
  arm64: dts: qcom: msm8916: Rename "x-smp2p" to "smp2p-x"
  arm64: dts: qcom: msm8916: Pad addresses
  arm64: dts: qcom: msm8916: Sort nodes
  arm64: dts: qcom: pm8916: Sort nodes
  arm64: dts: qcom: Makefile: Sort lines

 arch/arm64/boot/dts/qcom/Makefile             |   10 +-
 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi     |   12 +-
 .../qcom/msm8916-samsung-a2015-common.dtsi    |    2 +-
 .../boot/dts/qcom/msm8916-samsung-a3u-eur.dts |   12 +-
 arch/arm64/boot/dts/qcom/msm8916.dtsi         | 2571 ++++++++---------
 arch/arm64/boot/dts/qcom/pm8916.dtsi          |   84 +-
 6 files changed, 1339 insertions(+), 1352 deletions(-)

--
2.28.0
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[PATCH 01/14] arm64: dts: qcom: msm8916: Configure DSI port with labels Export this patch

Stephan Gerhold
&dsi0 -> ports -> port@1 -> endpoint already has the "dsi0_out" label,
so we can use it for configuring instead of replicating the entire
node hierarchy. Looks like I missed that when converting the boards.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
 arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi            | 12 +++---------
 arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts | 12 ++++--------
 2 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index d9af1a3785d8..3c7f97539390 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -292,15 +292,9 @@ ov5640_ep: endpoint {
	};
};

&dsi0 {
	ports {
		port@1 {
			endpoint {
				remote-endpoint = <&adv7533_in>;
				data-lanes = <0 1 2 3>;
			};
		};
	};
&dsi0_out {
	data-lanes = <0 1 2 3>;
	remote-endpoint = <&adv7533_in>;
};

&lpass {
diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
index 410c7d199f96..086f07ead5cb 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
@@ -44,15 +44,11 @@ panel_in: endpoint {
			};
		};
	};
};

	ports {
		port@1 {
			dsi0_out: endpoint {
				remote-endpoint = <&panel_in>;
				data-lanes = <0 1>;
			};
		};
	};
&dsi0_out {
	data-lanes = <0 1>;
	remote-endpoint = <&panel_in>;
};

&msmgpio {
-- 
2.28.0

[PATCH 02/14] arm64: dts: qcom: msm8916: Remove one more thermal trip point unit name Export this patch

Stephan Gerhold
Commit fe2aff0c574d2 ("arm64: dts: qcom: msm8916: remove unit name for thermal trip points")
removed the unit names for most of the thermal trip points defined
in msm8916.dtsi, but missed to update the one for cpu0_1-thermal.

So why wasn't this spotted by "make dtbs_check"? Apparently, the name
of the thermal zone is already invalid: thermal-zones.yaml specifies
a regex of ^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$, so it is not allowed
to contain underscores. Therefore the thermal zone was never verified
using the DTB schema.

After replacing the underscore in the thermal zone name, the warning
shows up:

    apq8016-sbc.dt.yaml: thermal-zones: cpu0-1-thermal:trips: 'trip-point@0'
    does not match any of the regexes: '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', 'pinctrl-[0-9]+'

Fix up the thermal zone names and remove the unit name for the trip point.

Cc: Amit Kucheria <amit.kucheria@linaro.org>
Fixes: fe2aff0c574d2 ("arm64: dts: qcom: msm8916: remove unit name for thermal trip points")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index d6a5b60846d9..d84118fb4403 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -229,14 +229,14 @@ pmu {
	};

	thermal-zones {
		cpu0_1-thermal {
		cpu0-1-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 5>;

			trips {
				cpu0_1_alert0: trip-point@0 {
				cpu0_1_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
@@ -259,7 +259,7 @@ map0 {
			};
		};

		cpu2_3-thermal {
		cpu2-3-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

-- 
2.28.0

[PATCH 03/14] arm64: dts: qcom: pm8916: Remove invalid reg size from wcd_codec Export this patch

Stephan Gerhold
Tha parent node of "wcd_codec" specifies #address-cells = <1>
and #size-cells = <0>, which means that each resource should be
described by one cell for the address and size omitted.

However, wcd_codec currently lists 0x200 as second cell (probably
the size of the resource). When parsing this would be treated like
another memory resource - which is entirely wrong.

To quote the device tree specification [1]:
  "If the parent node specifies a value of 0 for #size-cells,
   the length field in the value of reg shall be omitted."

[1]: https://www.devicetree.org/specifications/

Fixes: 5582fcb3829f ("arm64: dts: apq8016-sbc: add analog audio support with multicodec")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
 arch/arm64/boot/dts/qcom/pm8916.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi
index c3f62090aff7..636ef9db9a14 100644
--- a/arch/arm64/boot/dts/qcom/pm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -127,7 +127,7 @@ pm8916_vib: vibrator@c000 {

		wcd_codec: codec@f000 {
			compatible = "qcom,pm8916-wcd-analog-codec";
			reg = <0xf000 0x200>;
			reg = <0xf000>;
			reg-names = "pmic-codec-core";
			clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>;
			clock-names = "mclk";
-- 
2.28.0

[PATCH 04/14] arm64: dts: qcom: msm8916: Fix MDP/DSI interrupts Export this patch

Stephan Gerhold
The mdss node sets #interrupt-cells = <1>, so its interrupts
should be referenced using a single cell (in this case: only the
interrupt number).

However, right now the mdp/dsi node both have two interrupt cells
set, e.g. interrupts = <4 0>. The 0 is probably meant to say
IRQ_TYPE_NONE (= 0), but with #interrupt-cells = <1> this is
actually interpreted as a second interrupt line.

Remove the IRQ flags from both interrupts to fix this.

Fixes: 305410ffd1b2 ("arm64: dts: msm8916: Add display support")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index d84118fb4403..1f9a24a2464e 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1068,7 +1068,7 @@ mdp: mdp@1a01000 {
				reg-names = "mdp_phys";

				interrupt-parent = <&mdss>;
				interrupts = <0 0>;
				interrupts = <0>;

				clocks = <&gcc GCC_MDSS_AHB_CLK>,
					 <&gcc GCC_MDSS_AXI_CLK>,
@@ -1100,7 +1100,7 @@ dsi0: dsi@1a98000 {
				reg-names = "dsi_ctrl";

				interrupt-parent = <&mdss>;
				interrupts = <4 0>;
				interrupts = <4>;

				assigned-clocks = <&gcc BYTE0_CLK_SRC>,
						  <&gcc PCLK0_CLK_SRC>;
-- 
2.28.0

[PATCH 05/14] arm64: dts: qcom: msm8916: Use IRQ defines, add IRQ types Export this patch

Stephan Gerhold
dt-bindings/interrupt-controller/arm-gic.h has a GIC_SPI define
that allows specifying interrupts more clearly, but right now only
some device nodes in msm8916.dtsi make use of it.
Convert all others to use it.

The same applies to the IRQ_TYPE_* defines in
dt-bindings/interrupt-controller/irq.h. Some interrupts were defined
with raw numbers, or even with IRQ_TYPE_NONE (0).
Convert all these to use appropriate IRQ types.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 38 ++++++++++++++-------------
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 1f9a24a2464e..003451ccf3ee 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -737,7 +737,7 @@ lpass: lpass@7708000 {
					"mi2s-bit-clk3";
			#sound-dai-cells = <1>;

			interrupts = <0 160 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "lpass-irq-lpaif";
			reg = <0x07708000 0x10000>;
			reg-names = "lpass-lpaif";
@@ -760,7 +760,8 @@ sdhc_1: sdhci@7824000 {
			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>, <0 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
				 <&gcc GCC_SDCC1_AHB_CLK>,
@@ -777,7 +778,8 @@ sdhc_2: sdhci@7864000 {
			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, <0 221 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
				 <&gcc GCC_SDCC2_AHB_CLK>,
@@ -1053,7 +1055,7 @@ mdss: mdss@1a00000 {
				      "bus",
				      "vsync";

			interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-controller;
			#interrupt-cells = <1>;
@@ -1170,11 +1172,11 @@ mpss: hexagon@4080000 {

			reg-names = "qdsp6", "rmb";

			interrupts-extended = <&intc 0 24 1>,
					      <&hexagon_smp2p_in 0 0>,
					      <&hexagon_smp2p_in 1 0>,
					      <&hexagon_smp2p_in 2 0>,
					      <&hexagon_smp2p_in 3 0>;
			interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
					      <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";

@@ -1203,7 +1205,7 @@ mpss {
			};

			smd-edge {
				interrupts = <0 25 IRQ_TYPE_EDGE_RISING>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;

				qcom,smd-edge = <0>;
				qcom,ipc = <&apcs 8 12>;
@@ -1234,7 +1236,7 @@ pronto: wcnss@a21b000 {

			memory-region = <&wcnss_mem>;

			interrupts-extended = <&intc 0 149 IRQ_TYPE_EDGE_RISING>,
			interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
@@ -1257,7 +1259,7 @@ iris {
			};

			smd-edge {
				interrupts = <0 142 1>;
				interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;

				qcom,ipc = <&apcs 8 17>;
				qcom,smd-edge = <6>;
@@ -1278,8 +1280,8 @@ bt {
					wifi {
						compatible = "qcom,wcnss-wlan";

						interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>,
							     <0 146 IRQ_TYPE_LEVEL_HIGH>;
						interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
							     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
						interrupt-names = "tx", "rx";

						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
@@ -1836,7 +1838,7 @@ hexagon-smp2p {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;

		interrupts = <0 27 IRQ_TYPE_EDGE_RISING>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;

		qcom,ipc = <&apcs 8 14>;

@@ -1861,7 +1863,7 @@ wcnss-smp2p {
		compatible = "qcom,smp2p";
		qcom,smem = <451>, <431>;

		interrupts = <0 143 IRQ_TYPE_EDGE_RISING>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;

		qcom,ipc = <&apcs 8 18>;

@@ -1899,7 +1901,7 @@ apps_smsm: apps@0 {

		hexagon_smsm: hexagon@1 {
			reg = <1>;
			interrupts = <0 26 IRQ_TYPE_EDGE_RISING>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
@@ -1907,7 +1909,7 @@ hexagon_smsm: hexagon@1 {

		wcnss_smsm: wcnss@6 {
			reg = <6>;
			interrupts = <0 144 IRQ_TYPE_EDGE_RISING>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
-- 
2.28.0

[PATCH 06/14] arm64: dts: qcom: msm8916: Drop qcom,tcsr-mutex syscon Export this patch

Stephan Gerhold
The hwlock device node does not (directly) use memory resources
of the SoC, so we should move it outside the "soc" node.

However, as of commit 7a1e6fb1c606 ("hwspinlock: qcom: Allow mmio usage
in addition to syscon") we can now assign the memory region directly
to the hwlock device node. This works because the register space
used by it is actually separate and not used by any other components.
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 11 +++--------
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 003451ccf3ee..10e177988555 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -458,9 +458,10 @@ gcc: clock-controller@1800000 {
			reg = <0x1800000 0x80000>;
		};

		tcsr_mutex_regs: syscon@1905000 {
			compatible = "syscon";
		tcsr_mutex: hwlock@1905000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0x1905000 0x20000>;
			#hwlock-cells = <1>;
		};

		tcsr: syscon@1937000 {
@@ -468,12 +469,6 @@ tcsr: syscon@1937000 {
			reg = <0x1937000 0x30000>;
		};

		tcsr_mutex: hwlock {
			compatible = "qcom,tcsr-mutex";
			syscon = <&tcsr_mutex_regs 0 0x1000>;
			#hwlock-cells = <1>;
		};

		rpm_msg_ram: memory@60000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0x60000 0x8000>;
-- 
2.28.0

[PATCH 07/14] arm64: dts: qcom: msm8916: Minor style fixes Export this patch

Stephan Gerhold
Fix usages of spaces for indentation, break a long line
and remove duplicate new lines. Add some spaces where appropriate.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 10e177988555..eca3cd94d3d5 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -151,8 +151,8 @@ CPU3: cpu@3 {
		};

		L2_0: l2-cache {
		      compatible = "cache";
		      cache-level = <2>;
			compatible = "cache";
			cache-level = <2>;
		};

		idle-states {
@@ -225,7 +225,7 @@ CLUSTER_PD: power-domain-cluster {

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>;
		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	thermal-zones {
@@ -393,7 +393,9 @@ smem {
	firmware {
		scm: scm {
			compatible = "qcom,scm";
			clocks = <&gcc GCC_CRYPTO_CLK>, <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;
			clocks = <&gcc GCC_CRYPTO_CLK>,
				 <&gcc GCC_CRYPTO_AXI_CLK>,
				 <&gcc GCC_CRYPTO_AHB_CLK>;
			clock-names = "core", "bus", "iface";
			#reset-cells = <1>;

@@ -741,14 +743,14 @@ lpass: lpass@7708000 {
			#size-cells = <0>;
		};

                lpass_codec: codec{
		lpass_codec: codec@771c000 {
			compatible = "qcom,msm8916-wcd-digital-codec";
			reg = <0x0771c000 0x400>;
			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
				 <&gcc GCC_CODEC_DIGCODEC_CLK>;
			clock-names = "ahbix-clk", "mclk";
			#sound-dai-cells = <1>;
                };
		};

		sdhc_1: sdhci@7824000 {
			compatible = "qcom,sdhci-msm-v4";
@@ -1159,7 +1161,6 @@ dsi_phy0: dsi-phy@1a98300 {
			};
		};


		mpss: hexagon@4080000 {
			compatible = "qcom,q6v5-pil";
			reg = <0x04080000 0x100>,
@@ -1216,7 +1217,7 @@ fastrpc {
					#address-cells = <1>;
					#size-cells = <0>;

					cb@1{
					cb@1 {
						compatible = "qcom,fastrpc-compute-cb";
						reg = <1>;
					};
@@ -1474,7 +1475,7 @@ funnel1_out: endpoint {
		};

		debug0: debug@850000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x850000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
@@ -1483,7 +1484,7 @@ debug0: debug@850000 {
		};

		debug1: debug@852000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x852000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
@@ -1492,7 +1493,7 @@ debug1: debug@852000 {
		};

		debug2: debug@854000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x854000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
@@ -1501,7 +1502,7 @@ debug2: debug@854000 {
		};

		debug3: debug@856000 {
			compatible = "arm,coresight-cpu-debug","arm,primecell";
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x856000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
@@ -1679,7 +1680,6 @@ cti15: cti@85b000 {
			status = "disabled";
		};


		venus: video-codec@1d00000 {
			compatible = "qcom,msm8916-venus";
			reg = <0x01d00000 0xff000>;
-- 
2.28.0

[PATCH 08/14] arm64: dts: qcom: msm8916: Add MSM8916-specific compatibles to SCM/MSS Export this patch

Stephan Gerhold
Over the time, the SCM and MSS driver were refactored to use
SoC-specific compatibles. While the generic compatibles still work
correctly, add the MSM8916-specific compatibles so they are actually
used somewhere.

For SCM this will ensure that we actually manage to obtain all
three of the specified clocks, since those are required on MSM8916.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index eca3cd94d3d5..b2669643a12d 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -392,7 +392,7 @@ smem {

	firmware {
		scm: scm {
			compatible = "qcom,scm";
			compatible = "qcom,scm-msm8916", "qcom,scm";
			clocks = <&gcc GCC_CRYPTO_CLK>,
				 <&gcc GCC_CRYPTO_AXI_CLK>,
				 <&gcc GCC_CRYPTO_AHB_CLK>;
@@ -1162,7 +1162,7 @@ dsi_phy0: dsi-phy@1a98300 {
		};

		mpss: hexagon@4080000 {
			compatible = "qcom,q6v5-pil";
			compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
			reg = <0x04080000 0x100>,
			      <0x04020000 0x040>;

-- 
2.28.0

[PATCH 09/14] arm64: dts: qcom: msm8916: Use more generic node names Export this patch

Stephan Gerhold
Now that all MSM8916 boards are referencing nodes by label instead
of name, we can easily make some more nodes use more generic names
(as recommended in the device tree specification or the binding
documentation).

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
 .../qcom/msm8916-samsung-a2015-common.dtsi    |  2 +-
 arch/arm64/boot/dts/qcom/msm8916.dtsi         | 10 ++++-----
 arch/arm64/boot/dts/qcom/pm8916.dtsi          | 22 +++++++++----------
 3 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
index 2ba649bffd4e..b18d21e42f59 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
@@ -81,7 +81,7 @@ i2c-muic {
		#address-cells = <1>;
		#size-cells = <0>;

		muic: sm5502@25 {
		muic: extcon@25 {
			compatible = "siliconmitus,sm5502-muic";

			reg = <0x25>;
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index b2669643a12d..4444d068343c 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -714,7 +714,7 @@ sound: sound@7702000 {
			reg-names = "mic-iomux", "spkr-iomux";
		};

		lpass: lpass@7708000 {
		lpass: audio-controller@7708000 {
			status = "disabled";
			compatible = "qcom,lpass-cpu-apq8016";
			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
@@ -743,7 +743,7 @@ lpass: lpass@7708000 {
			#size-cells = <0>;
		};

		lpass_codec: codec@771c000 {
		lpass_codec: audio-codec@771c000 {
			compatible = "qcom,msm8916-wcd-digital-codec";
			reg = <0x0771c000 0x400>;
			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
@@ -1161,7 +1161,7 @@ dsi_phy0: dsi-phy@1a98300 {
			};
		};

		mpss: hexagon@4080000 {
		mpss: remoteproc@4080000 {
			compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
			reg = <0x04080000 0x100>,
			      <0x04020000 0x040>;
@@ -1225,7 +1225,7 @@ cb@1 {
			};
		};

		pronto: wcnss@a21b000 {
		pronto: remoteproc@a21b000 {
			compatible = "qcom,pronto-v2-pil", "qcom,pronto";
			reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
			reg-names = "ccu", "dxe", "pmu";
@@ -1821,7 +1821,7 @@ rpm_requests: rpm-requests {
				compatible = "qcom,rpm-msm8916";
				qcom,smd-channels = "rpm_requests";

				rpmcc: qcom,rpmcc {
				rpmcc: clock-controller {
					compatible = "qcom,rpmcc-msm8916";
					#clock-cells = <1>;
				};
diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi
index 636ef9db9a14..c7b22ac81452 100644
--- a/arch/arm64/boot/dts/qcom/pm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -6,7 +6,7 @@

&spmi_bus {

	pm8916_0: pm8916@0 {
	pm8916_0: pmic@0 {
		compatible = "qcom,pm8916", "qcom,spmi-pmic";
		reg = <0x0 SPMI_USID>;
		#address-cells = <1>;
@@ -79,7 +79,7 @@ pm8916_temp: temp-alarm@2400 {
			#thermal-sensor-cells = <0>;
		};

		pm8916_vadc: vadc@3100 {
		pm8916_vadc: adc@3100 {
			compatible = "qcom,spmi-vadc";
			reg = <0x3100>;
			interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
@@ -87,33 +87,33 @@ pm8916_vadc: vadc@3100 {
			#size-cells = <0>;
			#io-channel-cells = <1>;

			usb_in {
			adc-chan@0 {
				reg = <VADC_USBIN>;
				qcom,pre-scaling = <1 10>;
			};
			vph_pwr {
			adc-chan@7 {
				reg = <VADC_VSYS>;
				qcom,pre-scaling = <1 3>;
			};
			die_temp {
			adc-chan@8 {
				reg = <VADC_DIE_TEMP>;
			};
			ref_625mv {
			adc-chan@9 {
				reg = <VADC_REF_625MV>;
			};
			ref_1250v {
			adc-chan@a {
				reg = <VADC_REF_1250MV>;
			};
			ref_gnd {
			adc-chan@e {
				reg = <VADC_GND_REF>;
			};
			ref_vdd {
			adc-chan@f {
				reg = <VADC_VDD_VADC>;
			};
		};
	};

	pm8916_1: pm8916@1 {
	pm8916_1: pmic@1 {
		compatible = "qcom,pm8916", "qcom,spmi-pmic";
		reg = <0x1 SPMI_USID>;
		#address-cells = <1>;
@@ -125,7 +125,7 @@ pm8916_vib: vibrator@c000 {
			status = "disabled";
		};

		wcd_codec: codec@f000 {
		wcd_codec: audio-codec@f000 {
			compatible = "qcom,pm8916-wcd-analog-codec";
			reg = <0xf000>;
			reg-names = "pmic-codec-core";
-- 
2.28.0

[PATCH 10/14] arm64: dts: qcom: msm8916: Rename "x-smp2p" to "smp2p-x" Export this patch

Stephan Gerhold
This allows grouping them together when sorting nodes alphabetically.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 4444d068343c..47f01e206255 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1829,7 +1829,7 @@ rpmcc: clock-controller {
		};
	};

	hexagon-smp2p {
	smp2p-hexagon {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;

@@ -1854,7 +1854,7 @@ hexagon_smp2p_in: slave-kernel {
		};
	};

	wcnss-smp2p {
	smp2p-wcnss {
		compatible = "qcom,smp2p";
		qcom,smem = <451>, <431>;

-- 
2.28.0

[PATCH 11/14] arm64: dts: qcom: msm8916: Pad addresses Export this patch

Stephan Gerhold
Just like in commit 86f6d6225e5e ("arm64: dts: qcom: msm8996: Pad addresses"),
pad all addresses to 8 digits to make it easier to see the correct
order of the nodes.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 138 +++++++++++++-------------
 1 file changed, 69 insertions(+), 69 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 47f01e206255..9af528b9979b 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -420,7 +420,7 @@ bimc: interconnect@400000 {

		restart@4ab000 {
			compatible = "qcom,pshold";
			reg = <0x4ab000 0x4>;
			reg = <0x004ab000 0x4>;
		};

		pcnoc: interconnect@500000 {
@@ -443,7 +443,7 @@ snoc: interconnect@580000 {

		msmgpio: pinctrl@1000000 {
			compatible = "qcom,msm8916-pinctrl";
			reg = <0x1000000 0x300000>;
			reg = <0x01000000 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			gpio-ranges = <&msmgpio 0 0 122>;
@@ -457,28 +457,28 @@ gcc: clock-controller@1800000 {
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x1800000 0x80000>;
			reg = <0x01800000 0x80000>;
		};

		tcsr_mutex: hwlock@1905000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0x1905000 0x20000>;
			reg = <0x01905000 0x20000>;
			#hwlock-cells = <1>;
		};

		tcsr: syscon@1937000 {
			compatible = "qcom,tcsr-msm8916", "syscon";
			reg = <0x1937000 0x30000>;
			reg = <0x01937000 0x30000>;
		};

		rpm_msg_ram: memory@60000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0x60000 0x8000>;
			reg = <0x00060000 0x8000>;
		};

		blsp1_uart1: serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78af000 0x200>;
			reg = <0x078af000 0x200>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
@@ -492,13 +492,13 @@ blsp1_uart1: serial@78af000 {

		a53pll: clock@b016000 {
			compatible = "qcom,msm8916-a53pll";
			reg = <0xb016000 0x40>;
			reg = <0x0b016000 0x40>;
			#clock-cells = <0>;
		};

		apcs: mailbox@b011000 {
			compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
			reg = <0xb011000 0x1000>;
			reg = <0x0b011000 0x1000>;
			#mbox-cells = <1>;
			clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
			clock-names = "pll", "aux";
@@ -507,7 +507,7 @@ apcs: mailbox@b011000 {

		blsp1_uart2: serial@78b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78b0000 0x200>;
			reg = <0x078b0000 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
@@ -788,8 +788,8 @@ sdhc_2: sdhci@7864000 {

		usb: usb@78d9000 {
			compatible = "qcom,ci-hdrc";
			reg = <0x78d9000 0x200>,
			      <0x78d9200 0x200>;
			reg = <0x078d9000 0x200>,
			      <0x078d9200 0x200>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
@@ -837,67 +837,67 @@ timer@b020000 {
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xb020000 0x1000>;
			reg = <0x0b020000 0x1000>;
			clock-frequency = <19200000>;

			frame@b021000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb021000 0x1000>,
				      <0xb022000 0x1000>;
				reg = <0x0b021000 0x1000>,
				      <0x0b022000 0x1000>;
			};

			frame@b023000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb023000 0x1000>;
				reg = <0x0b023000 0x1000>;
				status = "disabled";
			};

			frame@b024000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb024000 0x1000>;
				reg = <0x0b024000 0x1000>;
				status = "disabled";
			};

			frame@b025000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb025000 0x1000>;
				reg = <0x0b025000 0x1000>;
				status = "disabled";
			};

			frame@b026000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb026000 0x1000>;
				reg = <0x0b026000 0x1000>;
				status = "disabled";
			};

			frame@b027000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb027000 0x1000>;
				reg = <0x0b027000 0x1000>;
				status = "disabled";
			};

			frame@b028000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0xb028000 0x1000>;
				reg = <0x0b028000 0x1000>;
				status = "disabled";
			};
		};

		spmi_bus: spmi@200f000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x200f000 0x001000>,
			      <0x2400000 0x400000>,
			      <0x2c00000 0x400000>,
			      <0x3800000 0x200000>,
			      <0x200a000 0x002100>;
			reg = <0x0200f000 0x001000>,
			      <0x02400000 0x400000>,
			      <0x02c00000 0x400000>,
			      <0x03800000 0x200000>,
			      <0x0200a000 0x002100>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
@@ -918,7 +918,7 @@ rng@22000 {

		qfprom: qfprom@5c000 {
			compatible = "qcom,qfprom";
			reg = <0x5c000 0x1000>;
			reg = <0x0005c000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			tsens_caldata: caldata@d0 {
@@ -931,8 +931,8 @@ tsens_calsel: calsel@ec {

		tsens: thermal-sensor@4a9000 {
			compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
			reg = <0x4a9000 0x1000>, /* TM */
			      <0x4a8000 0x1000>; /* SROT */
			reg = <0x004a9000 0x1000>, /* TM */
			      <0x004a8000 0x1000>; /* SROT */
			nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
			nvmem-cell-names = "calib", "calib_sel";
			#qcom,sensors = <5>;
@@ -946,8 +946,8 @@ apps_iommu: iommu@1ef0000 {
			#size-cells = <1>;
			#iommu-cells = <1>;
			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
			ranges = <0 0x1e20000 0x40000>;
			reg = <0x1ef0000 0x3000>;
			ranges = <0 0x01e20000 0x40000>;
			reg = <0x01ef0000 0x3000>;
			clocks = <&gcc GCC_SMMU_CFG_CLK>,
				 <&gcc GCC_APSS_TCU_CLK>;
			clock-names = "iface", "bus";
@@ -980,7 +980,7 @@ gpu_iommu: iommu@1f08000 {
			#size-cells = <1>;
			#iommu-cells = <1>;
			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
			ranges = <0 0x1f08000 0x10000>;
			ranges = <0 0x01f08000 0x10000>;
			clocks = <&gcc GCC_SMMU_CFG_CLK>,
				 <&gcc GCC_GFX_TCU_CLK>;
			clock-names = "iface", "bus";
@@ -1039,8 +1039,8 @@ opp-19200000 {

		mdss: mdss@1a00000 {
			compatible = "qcom,mdss";
			reg = <0x1a00000 0x1000>,
			      <0x1ac8000 0x3000>;
			reg = <0x01a00000 0x1000>,
			      <0x01ac8000 0x3000>;
			reg-names = "mdss_phys", "vbif_phys";

			power-domains = <&gcc MDSS_GDSC>;
@@ -1063,7 +1063,7 @@ mdss: mdss@1a00000 {

			mdp: mdp@1a01000 {
				compatible = "qcom,mdp5";
				reg = <0x1a01000 0x89000>;
				reg = <0x01a01000 0x89000>;
				reg-names = "mdp_phys";

				interrupt-parent = <&mdss>;
@@ -1095,7 +1095,7 @@ mdp5_intf1_out: endpoint {

			dsi0: dsi@1a98000 {
				compatible = "qcom,mdss-dsi-ctrl";
				reg = <0x1a98000 0x25c>;
				reg = <0x01a98000 0x25c>;
				reg-names = "dsi_ctrl";

				interrupt-parent = <&mdss>;
@@ -1145,9 +1145,9 @@ dsi0_out: endpoint {

			dsi_phy0: dsi-phy@1a98300 {
				compatible = "qcom,dsi-phy-28nm-lp";
				reg = <0x1a98300 0xd4>,
				      <0x1a98500 0x280>,
				      <0x1a98780 0x30>;
				reg = <0x01a98300 0xd4>,
				      <0x01a98500 0x280>,
				      <0x01a98780 0x30>;
				reg-names = "dsi_pll",
					    "dsi_phy",
					    "dsi_phy_regulator";
@@ -1289,7 +1289,7 @@ wifi {

		tpiu: tpiu@820000 {
			compatible = "arm,coresight-tpiu", "arm,primecell";
			reg = <0x820000 0x1000>;
			reg = <0x00820000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
@@ -1307,7 +1307,7 @@ tpiu_in: endpoint {

		funnel0: funnel@821000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x821000 0x1000>;
			reg = <0x00821000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
@@ -1348,7 +1348,7 @@ funnel0_out: endpoint {

		replicator: replicator@824000 {
			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
			reg = <0x824000 0x1000>;
			reg = <0x00824000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
@@ -1384,7 +1384,7 @@ replicator_in: endpoint {

		etf: etf@825000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x825000 0x1000>;
			reg = <0x00825000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
@@ -1410,7 +1410,7 @@ etf_out: endpoint {

		etr: etr@826000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x826000 0x1000>;
			reg = <0x00826000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
@@ -1428,7 +1428,7 @@ etr_in: endpoint {

		funnel1: funnel@841000 {	/* APSS funnel only 4 inputs are used */
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x841000 0x1000>;
			reg = <0x00841000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
@@ -1476,7 +1476,7 @@ funnel1_out: endpoint {

		debug0: debug@850000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x850000 0x1000>;
			reg = <0x00850000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU0>;
@@ -1485,7 +1485,7 @@ debug0: debug@850000 {

		debug1: debug@852000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x852000 0x1000>;
			reg = <0x00852000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU1>;
@@ -1494,7 +1494,7 @@ debug1: debug@852000 {

		debug2: debug@854000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x854000 0x1000>;
			reg = <0x00854000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU2>;
@@ -1503,7 +1503,7 @@ debug2: debug@854000 {

		debug3: debug@856000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x856000 0x1000>;
			reg = <0x00856000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU3>;
@@ -1512,7 +1512,7 @@ debug3: debug@856000 {

		etm0: etm@85c000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x85c000 0x1000>;
			reg = <0x0085c000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
@@ -1533,7 +1533,7 @@ etm0_out: endpoint {

		etm1: etm@85d000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x85d000 0x1000>;
			reg = <0x0085d000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
@@ -1554,7 +1554,7 @@ etm1_out: endpoint {

		etm2: etm@85e000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x85e000 0x1000>;
			reg = <0x0085e000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
@@ -1575,7 +1575,7 @@ etm2_out: endpoint {

		etm3: etm@85f000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x85f000 0x1000>;
			reg = <0x0085f000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
@@ -1598,7 +1598,7 @@ etm3_out: endpoint {
		/* CTI 0 - TMC connections */
		cti0: cti@810000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x810000 0x1000>;
			reg = <0x00810000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
@@ -1609,7 +1609,7 @@ cti0: cti@810000 {
		/* CTI 1 - TPIU connections */
		cti1: cti@811000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x811000 0x1000>;
			reg = <0x00811000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
@@ -1624,7 +1624,7 @@ cti1: cti@811000 {
		cti12: cti@858000 {
			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
				     "arm,primecell";
			reg = <0x858000 0x1000>;
			reg = <0x00858000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
@@ -1639,7 +1639,7 @@ cti12: cti@858000 {
		cti13: cti@859000 {
			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
				     "arm,primecell";
			reg = <0x859000 0x1000>;
			reg = <0x00859000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
@@ -1654,7 +1654,7 @@ cti13: cti@859000 {
		cti14: cti@85a000 {
			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
				     "arm,primecell";
			reg = <0x85a000 0x1000>;
			reg = <0x0085a000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
@@ -1669,7 +1669,7 @@ cti14: cti@85a000 {
		cti15: cti@85b000 {
			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
				     "arm,primecell";
			reg = <0x85b000 0x1000>;
			reg = <0x0085b000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
@@ -1704,15 +1704,15 @@ video-encoder {

		camss: camss@1b00000 {
			compatible = "qcom,msm8916-camss";
			reg = <0x1b0ac00 0x200>,
				<0x1b00030 0x4>,
				<0x1b0b000 0x200>,
				<0x1b00038 0x4>,
				<0x1b08000 0x100>,
				<0x1b08400 0x100>,
				<0x1b0a000 0x500>,
				<0x1b00020 0x10>,
				<0x1b10000 0x1000>;
			reg = <0x01b0ac00 0x200>,
				<0x01b00030 0x4>,
				<0x01b0b000 0x200>,
				<0x01b00038 0x4>,
				<0x01b08000 0x100>,
				<0x01b08400 0x100>,
				<0x01b0a000 0x500>,
				<0x01b00020 0x10>,
				<0x01b10000 0x1000>;
			reg-names = "csiphy0",
				"csiphy0_clk_mux",
				"csiphy1",
@@ -1785,7 +1785,7 @@ cci: cci@1b0c000 {
			compatible = "qcom,msm8916-cci";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x1b0c000 0x1000>;
			reg = <0x01b0c000 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
				<&gcc GCC_CAMSS_CCI_AHB_CLK>,
-- 
2.28.0

[PATCH 12/14] arm64: dts: qcom: msm8916: Sort nodes Export this patch

Stephan Gerhold
Just like in commit 50aa72ccb30b ("arm64: dts: qcom: msm8996:
Sort all nodes in msm8996.dtsi"), sort all the nodes by unit address,
then alphabetically by their name.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 2540 ++++++++++++-------------
 1 file changed, 1270 insertions(+), 1270 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 9af528b9979b..aaa21899f1a6 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -4,11 +4,11 @@
 */

#include <dt-bindings/arm/coresight-cti-dt.h>
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/interconnect/qcom,msm8916.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8916.h>
#include <dt-bindings/reset/qcom,gcc-msm8916.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/thermal/thermal.h>

/ {
@@ -94,6 +94,20 @@ mba_mem: mba@8ea00000 {
		};
	};

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
@@ -189,6 +203,42 @@ CLUSTER_PWRDN: cluster-gdhs {
		};
	};

	cpu_opp_table: cpu-opp-table {
		compatible = "operating-points-v2";
		opp-shared;

		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
		};
		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
		};
		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
		};
		opp-998400000 {
			opp-hz = /bits/ 64 <998400000>;
		};
	};

	firmware {
		scm: scm {
			compatible = "qcom,scm-msm8916", "qcom,scm";
			clocks = <&gcc GCC_CRYPTO_CLK>,
				 <&gcc GCC_CRYPTO_AXI_CLK>,
				 <&gcc GCC_CRYPTO_AHB_CLK>;
			clock-names = "core", "bus", "iface";
			#reset-cells = <1>;

			qcom,dload-mode = <&tcsr 0x6100>;
		};
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
@@ -223,183 +273,114 @@ CLUSTER_PD: power-domain-cluster {
		};
	};

	pmu {
		compatible = "arm,cortex-a53-pmu";
		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	thermal-zones {
		cpu0-1-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
	smd {
		compatible = "qcom,smd";

			thermal-sensors = <&tsens 5>;
		rpm {
			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;

			trips {
				cpu0_1_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu0_1_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
			rpm_requests: rpm-requests {
				compatible = "qcom,rpm-msm8916";
				qcom,smd-channels = "rpm_requests";

			cooling-maps {
				map0 {
					trip = <&cpu0_1_alert0>;
					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				rpmcc: clock-controller {
					compatible = "qcom,rpmcc-msm8916";
					#clock-cells = <1>;
				};
			};
		};
	};

		cpu2-3-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 4>;
	smem {
		compatible = "qcom,smem";

			trips {
				cpu2_3_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu2_3_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		memory-region = <&smem_mem>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;

			cooling-maps {
				map0 {
					trip = <&cpu2_3_alert0>;
					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
		hwlocks = <&tcsr_mutex 3>;
	};

		gpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
	smp2p-hexagon {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;

			thermal-sensors = <&tsens 2>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;

			trips {
				gpu_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				gpu_crit: gpu_crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
		qcom,ipc = <&apcs 8 14>;

		camera-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

			thermal-sensors = <&tsens 1>;
		hexagon_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";

			trips {
				cam_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
			#qcom,smem-state-cells = <1>;
		};

		modem-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			thermal-sensors = <&tsens 0>;
		hexagon_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			trips {
				modem_alert0: trip-point0 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
			interrupt-controller;
			#interrupt-cells = <2>;
		};

	};

	cpu_opp_table: cpu-opp-table {
		compatible = "operating-points-v2";
		opp-shared;
	smp2p-wcnss {
		compatible = "qcom,smp2p";
		qcom,smem = <451>, <431>;

		opp-200000000 {
			opp-hz = /bits/ 64 <200000000>;
		};
		opp-400000000 {
			opp-hz = /bits/ 64 <400000000>;
		};
		opp-800000000 {
			opp-hz = /bits/ 64 <800000000>;
		};
		opp-998400000 {
			opp-hz = /bits/ 64 <998400000>;
		};
	};
		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};
		qcom,ipc = <&apcs 8 18>;

	clocks {
		xo_board: xo-board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <4>;

		wcnss_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";

			#qcom,smem-state-cells = <1>;
		};

		sleep_clk: sleep-clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		wcnss_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	smem {
		compatible = "qcom,smem";
	smsm {
		compatible = "qcom,smsm";

		memory-region = <&smem_mem>;
		qcom,rpm-msg-ram = <&rpm_msg_ram>;
		#address-cells = <1>;
		#size-cells = <0>;

		hwlocks = <&tcsr_mutex 3>;
	};
		qcom,ipc-1 = <&apcs 8 13>;
		qcom,ipc-3 = <&apcs 8 19>;

	firmware {
		scm: scm {
			compatible = "qcom,scm-msm8916", "qcom,scm";
			clocks = <&gcc GCC_CRYPTO_CLK>,
				 <&gcc GCC_CRYPTO_AXI_CLK>,
				 <&gcc GCC_CRYPTO_AHB_CLK>;
			clock-names = "core", "bus", "iface";
			#reset-cells = <1>;
		apps_smsm: apps@0 {
			reg = <0>;

			qcom,dload-mode = <&tcsr 0x6100>;
			#qcom,smem-state-cells = <1>;
		};

		hexagon_smsm: hexagon@1 {
			reg = <1>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};

		wcnss_smsm: wcnss@6 {
			reg = <6>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

@@ -409,6 +390,36 @@ soc: soc {
		ranges = <0 0 0 0xffffffff>;
		compatible = "simple-bus";

		rng@22000 {
			compatible = "qcom,prng";
			reg = <0x00022000 0x200>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};

		restart@4ab000 {
			compatible = "qcom,pshold";
			reg = <0x004ab000 0x4>;
		};

		qfprom: qfprom@5c000 {
			compatible = "qcom,qfprom";
			reg = <0x0005c000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			tsens_caldata: caldata@d0 {
				reg = <0xd0 0x8>;
			};
			tsens_calsel: calsel@ec {
				reg = <0xec 0x4>;
			};
		};

		rpm_msg_ram: memory@60000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0x00060000 0x8000>;
		};

		bimc: interconnect@400000 {
			compatible = "qcom,msm8916-bimc";
			reg = <0x00400000 0x62000>;
@@ -418,9 +429,16 @@ bimc: interconnect@400000 {
				 <&rpmcc RPM_SMD_BIMC_A_CLK>;
		};

		restart@4ab000 {
			compatible = "qcom,pshold";
			reg = <0x004ab000 0x4>;
		tsens: thermal-sensor@4a9000 {
			compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
			reg = <0x004a9000 0x1000>, /* TM */
			      <0x004a8000 0x1000>; /* SROT */
			nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
			nvmem-cell-names = "calib", "calib_sel";
			#qcom,sensors = <5>;
			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow";
			#thermal-sensor-cells = <1>;
		};

		pcnoc: interconnect@500000 {
@@ -441,602 +459,429 @@ snoc: interconnect@580000 {
				 <&rpmcc RPM_SMD_SNOC_A_CLK>;
		};

		msmgpio: pinctrl@1000000 {
			compatible = "qcom,msm8916-pinctrl";
			reg = <0x01000000 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			gpio-ranges = <&msmgpio 0 0 122>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};
		/* System CTIs */
		/* CTI 0 - TMC connections */
		cti0: cti@810000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x00810000 0x1000>;

		gcc: clock-controller@1800000 {
			compatible = "qcom,gcc-msm8916";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x01800000 0x80000>;
		};
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

		tcsr_mutex: hwlock@1905000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0x01905000 0x20000>;
			#hwlock-cells = <1>;
			status = "disabled";
		};

		tcsr: syscon@1937000 {
			compatible = "qcom,tcsr-msm8916", "syscon";
			reg = <0x01937000 0x30000>;
		};
		/* CTI 1 - TPIU connections */
		cti1: cti@811000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x00811000 0x1000>;

		rpm_msg_ram: memory@60000 {
			compatible = "qcom,rpm-msg-ram";
			reg = <0x00060000 0x8000>;
		};
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

		blsp1_uart1: serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078af000 0x200>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 1>, <&blsp_dma 0>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_uart1_default>;
			pinctrl-1 = <&blsp1_uart1_sleep>;
			status = "disabled";
		};

		a53pll: clock@b016000 {
			compatible = "qcom,msm8916-a53pll";
			reg = <0x0b016000 0x40>;
			#clock-cells = <0>;
		};
		/* CTIs 2-11 - no information - not instantiated */

		apcs: mailbox@b011000 {
			compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
			reg = <0x0b011000 0x1000>;
			#mbox-cells = <1>;
			clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
			clock-names = "pll", "aux";
			#clock-cells = <0>;
		};
		tpiu: tpiu@820000 {
			compatible = "arm,coresight-tpiu", "arm,primecell";
			reg = <0x00820000 0x1000>;

		blsp1_uart2: serial@78b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078b0000 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 3>, <&blsp_dma 2>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_uart2_default>;
			pinctrl-1 = <&blsp1_uart2_sleep>;
			status = "disabled";
		};
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

		blsp_dma: dma@7884000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07884000 0x23000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";
		};

		blsp_spi1: spi@78b5000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b5000 0x500>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 5>, <&blsp_dma 4>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi1_default>;
			pinctrl-1 = <&spi1_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
			in-ports {
				port {
					tpiu_in: endpoint {
						remote-endpoint = <&replicator_out1>;
					};
				};
			};
		};

		blsp_spi2: spi@78b6000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b6000 0x500>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 7>, <&blsp_dma 6>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi2_default>;
			pinctrl-1 = <&spi2_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		funnel0: funnel@821000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x00821000 0x1000>;

		blsp_spi3: spi@78b7000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b7000 0x500>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 9>, <&blsp_dma 8>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi3_default>;
			pinctrl-1 = <&spi3_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

		blsp_spi4: spi@78b8000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b8000 0x500>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 11>, <&blsp_dma 10>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi4_default>;
			pinctrl-1 = <&spi4_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		blsp_spi5: spi@78b9000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b9000 0x500>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 13>, <&blsp_dma 12>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi5_default>;
			pinctrl-1 = <&spi5_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

		blsp_spi6: spi@78ba000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078ba000 0x500>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 15>, <&blsp_dma 14>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi6_default>;
			pinctrl-1 = <&spi6_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
				/*
				 * Not described input ports:
				 * 0 - connected to Resource and Power Manger CPU ETM
				 * 1 - not-connected
				 * 2 - connected to Modem CPU ETM
				 * 3 - not-connected
				 * 5 - not-connected
				 * 6 - connected trought funnel to Wireless CPU ETM
				 * 7 - connected to STM component
				 */

		blsp_i2c1: i2c@78b5000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b5000 0x500>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c1_default>;
			pinctrl-1 = <&i2c1_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
				port@4 {
					reg = <4>;
					funnel0_in4: endpoint {
						remote-endpoint = <&funnel1_out>;
					};
				};
			};

		blsp_i2c2: i2c@78b6000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b6000 0x500>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c2_default>;
			pinctrl-1 = <&i2c2_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
			out-ports {
				port {
					funnel0_out: endpoint {
						remote-endpoint = <&etf_in>;
					};
				};
			};
		};

		blsp_i2c4: i2c@78b8000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b8000 0x500>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c4_default>;
			pinctrl-1 = <&i2c4_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
		replicator: replicator@824000 {
			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
			reg = <0x00824000 0x1000>;

		blsp_i2c5: i2c@78b9000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b9000 0x500>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c5_default>;
			pinctrl-1 = <&i2c5_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

		blsp_i2c6: i2c@78ba000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078ba000 0x500>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c6_default>;
			pinctrl-1 = <&i2c6_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		sound: sound@7702000 {
			status = "disabled";
			compatible = "qcom,apq8016-sbc-sndcard";
			reg = <0x07702000 0x4>, <0x07702004 0x4>;
			reg-names = "mic-iomux", "spkr-iomux";
			out-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					replicator_out0: endpoint {
						remote-endpoint = <&etr_in>;
					};
				};
				port@1 {
					reg = <1>;
					replicator_out1: endpoint {
						remote-endpoint = <&tpiu_in>;
					};
				};
			};

			in-ports {
				port {
					replicator_in: endpoint {
						remote-endpoint = <&etf_out>;
					};
				};
			};
		};

		lpass: audio-controller@7708000 {
			status = "disabled";
			compatible = "qcom,lpass-cpu-apq8016";
			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
				 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
				 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;
		etf: etf@825000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x00825000 0x1000>;

			clock-names = "ahbix-clk",
					"pcnoc-mport-clk",
					"pcnoc-sway-clk",
					"mi2s-bit-clk0",
					"mi2s-bit-clk1",
					"mi2s-bit-clk2",
					"mi2s-bit-clk3";
			#sound-dai-cells = <1>;
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "lpass-irq-lpaif";
			reg = <0x07708000 0x10000>;
			reg-names = "lpass-lpaif";
			status = "disabled";

			#address-cells = <1>;
			#size-cells = <0>;
		};
			in-ports {
				port {
					etf_in: endpoint {
						remote-endpoint = <&funnel0_out>;
					};
				};
			};

		lpass_codec: audio-codec@771c000 {
			compatible = "qcom,msm8916-wcd-digital-codec";
			reg = <0x0771c000 0x400>;
			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
				 <&gcc GCC_CODEC_DIGCODEC_CLK>;
			clock-names = "ahbix-clk", "mclk";
			#sound-dai-cells = <1>;
			out-ports {
				port {
					etf_out: endpoint {
						remote-endpoint = <&replicator_in>;
					};
				};
			};
		};

		sdhc_1: sdhci@7824000 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
			reg-names = "hc_mem", "core_mem";
		etr: etr@826000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x00826000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
				 <&gcc GCC_SDCC1_AHB_CLK>,
				 <&xo_board>;
			clock-names = "core", "iface", "xo";
			mmc-ddr-1_8v;
			bus-width = <8>;
			non-removable;
			status = "disabled";

			in-ports {
				port {
					etr_in: endpoint {
						remote-endpoint = <&replicator_out0>;
					};
				};
			};
		};

		sdhc_2: sdhci@7864000 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
			reg-names = "hc_mem", "core_mem";
		funnel1: funnel@841000 {	/* APSS funnel only 4 inputs are used */
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x00841000 0x1000>;

			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
				 <&gcc GCC_SDCC2_AHB_CLK>,
				 <&xo_board>;
			clock-names = "core", "iface", "xo";
			bus-width = <4>;
			status = "disabled";
		};
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

		usb: usb@78d9000 {
			compatible = "qcom,ci-hdrc";
			reg = <0x078d9000 0x200>,
			      <0x078d9200 0x200>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
			clock-names = "iface", "core";
			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
			assigned-clock-rates = <80000000>;
			resets = <&gcc GCC_USB_HS_BCR>;
			reset-names = "core";
			phy_type = "ulpi";
			dr_mode = "otg";
			hnp-disable;
			srp-disable;
			adp-disable;
			ahb-burst-config = <0>;
			phy-names = "usb-phy";
			phys = <&usb_hs_phy>;
			status = "disabled";
			#reset-cells = <1>;

			ulpi {
				usb_hs_phy: phy {
					compatible = "qcom,usb-hs-phy-msm8916",
						     "qcom,usb-hs-phy";
					#phy-cells = <0>;
					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
					clock-names = "ref", "sleep";
					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
					reset-names = "phy", "por";
					qcom,init-seq = /bits/ 8 <0x0 0x44
						0x1 0x6b 0x2 0x24 0x3 0x13>;
			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					funnel1_in0: endpoint {
						remote-endpoint = <&etm0_out>;
					};
				};
				port@1 {
					reg = <1>;
					funnel1_in1: endpoint {
						remote-endpoint = <&etm1_out>;
					};
				};
				port@2 {
					reg = <2>;
					funnel1_in2: endpoint {
						remote-endpoint = <&etm2_out>;
					};
				};
				port@3 {
					reg = <3>;
					funnel1_in3: endpoint {
						remote-endpoint = <&etm3_out>;
					};
				};
			};
		};

		intc: interrupt-controller@b000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
			out-ports {
				port {
					funnel1_out: endpoint {
						remote-endpoint = <&funnel0_in4>;
					};
				};
			};
		};

		timer@b020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x0b020000 0x1000>;
			clock-frequency = <19200000>;
		debug0: debug@850000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x00850000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU0>;
			status = "disabled";
		};

			frame@b021000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b021000 0x1000>,
				      <0x0b022000 0x1000>;
			};
		debug1: debug@852000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x00852000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU1>;
			status = "disabled";
		};

			frame@b023000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b023000 0x1000>;
				status = "disabled";
			};
		debug2: debug@854000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x00854000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU2>;
			status = "disabled";
		};

			frame@b024000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b024000 0x1000>;
				status = "disabled";
			};
		debug3: debug@856000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x00856000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU3>;
			status = "disabled";
		};

			frame@b025000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b025000 0x1000>;
				status = "disabled";
			};
		/* Core CTIs; CTIs 12-15 */
		/* CTI - CPU-0 */
		cti12: cti@858000 {
			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
				     "arm,primecell";
			reg = <0x00858000 0x1000>;

			frame@b026000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b026000 0x1000>;
				status = "disabled";
			};
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

			frame@b027000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b027000 0x1000>;
				status = "disabled";
			};
			cpu = <&CPU0>;
			arm,cs-dev-assoc = <&etm0>;

			frame@b028000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b028000 0x1000>;
				status = "disabled";
			};
			status = "disabled";
		};

		spmi_bus: spmi@200f000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x0200f000 0x001000>,
			      <0x02400000 0x400000>,
			      <0x02c00000 0x400000>,
			      <0x03800000 0x200000>,
			      <0x0200a000 0x002100>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};
		/* CTI - CPU-1 */
		cti13: cti@859000 {
			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
				     "arm,primecell";
			reg = <0x00859000 0x1000>;

		rng@22000 {
			compatible = "qcom,prng";
			reg = <0x00022000 0x200>;
			clocks = <&gcc GCC_PRNG_AHB_CLK>;
			clock-names = "core";
		};
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

		qfprom: qfprom@5c000 {
			compatible = "qcom,qfprom";
			reg = <0x0005c000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			tsens_caldata: caldata@d0 {
				reg = <0xd0 0x8>;
			};
			tsens_calsel: calsel@ec {
				reg = <0xec 0x4>;
			};
		};
			cpu = <&CPU1>;
			arm,cs-dev-assoc = <&etm1>;

		tsens: thermal-sensor@4a9000 {
			compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1";
			reg = <0x004a9000 0x1000>, /* TM */
			      <0x004a8000 0x1000>; /* SROT */
			nvmem-cells = <&tsens_caldata>, <&tsens_calsel>;
			nvmem-cell-names = "calib", "calib_sel";
			#qcom,sensors = <5>;
			interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "uplow";
			#thermal-sensor-cells = <1>;
			status = "disabled";
		};

		apps_iommu: iommu@1ef0000 {
			#address-cells = <1>;
			#size-cells = <1>;
			#iommu-cells = <1>;
			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
			ranges = <0 0x01e20000 0x40000>;
			reg = <0x01ef0000 0x3000>;
			clocks = <&gcc GCC_SMMU_CFG_CLK>,
				 <&gcc GCC_APSS_TCU_CLK>;
			clock-names = "iface", "bus";
			qcom,iommu-secure-id = <17>;
		/* CTI - CPU-2 */
		cti14: cti@85a000 {
			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
				     "arm,primecell";
			reg = <0x0085a000 0x1000>;

			// vfe:
			iommu-ctx@3000 {
				compatible = "qcom,msm-iommu-v1-sec";
				reg = <0x3000 0x1000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			};
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

			// mdp_0:
			iommu-ctx@4000 {
				compatible = "qcom,msm-iommu-v1-ns";
				reg = <0x4000 0x1000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			};
			cpu = <&CPU2>;
			arm,cs-dev-assoc = <&etm2>;

			// venus_ns:
			iommu-ctx@5000 {
				compatible = "qcom,msm-iommu-v1-sec";
				reg = <0x5000 0x1000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			};
			status = "disabled";
		};

		gpu_iommu: iommu@1f08000 {
			#address-cells = <1>;
			#size-cells = <1>;
			#iommu-cells = <1>;
			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
			ranges = <0 0x01f08000 0x10000>;
			clocks = <&gcc GCC_SMMU_CFG_CLK>,
				 <&gcc GCC_GFX_TCU_CLK>;
			clock-names = "iface", "bus";
			qcom,iommu-secure-id = <18>;
		/* CTI - CPU-3 */
		cti15: cti@85b000 {
			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
				     "arm,primecell";
			reg = <0x0085b000 0x1000>;

			// gfx3d_user:
			iommu-ctx@1000 {
				compatible = "qcom,msm-iommu-v1-ns";
				reg = <0x1000 0x1000>;
				interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

			cpu = <&CPU3>;
			arm,cs-dev-assoc = <&etm3>;

			status = "disabled";
		};

		etm0: etm@85c000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x0085c000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
			arm,coresight-loses-context-with-cpu;

			cpu = <&CPU0>;

			status = "disabled";

			out-ports {
				port {
					etm0_out: endpoint {
						remote-endpoint = <&funnel1_in0>;
					};
				};
			};
		};

			// gfx3d_priv:
			iommu-ctx@2000 {
				compatible = "qcom,msm-iommu-v1-ns";
				reg = <0x2000 0x1000>;
				interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
		etm1: etm@85d000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x0085d000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
			arm,coresight-loses-context-with-cpu;

			cpu = <&CPU1>;

			status = "disabled";

			out-ports {
				port {
					etm1_out: endpoint {
						remote-endpoint = <&funnel1_in1>;
					};
				};
			};
		};

		gpu@1c00000 {
			compatible = "qcom,adreno-306.0", "qcom,adreno";
			reg = <0x01c00000 0x20000>;
			reg-names = "kgsl_3d0_reg_memory";
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "kgsl_3d0_irq";
			clock-names =
			    "core",
			    "iface",
			    "mem",
			    "mem_iface",
			    "alt_mem_iface",
			    "gfx3d";
			clocks =
			    <&gcc GCC_OXILI_GFX3D_CLK>,
			    <&gcc GCC_OXILI_AHB_CLK>,
			    <&gcc GCC_OXILI_GMEM_CLK>,
			    <&gcc GCC_BIMC_GFX_CLK>,
			    <&gcc GCC_BIMC_GPU_CLK>,
			    <&gcc GFX3D_CLK_SRC>;
			power-domains = <&gcc OXILI_GDSC>;
			operating-points-v2 = <&gpu_opp_table>;
			iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
		etm2: etm@85e000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x0085e000 0x1000>;

			gpu_opp_table: opp-table {
				compatible = "operating-points-v2";
			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
			arm,coresight-loses-context-with-cpu;

				opp-400000000 {
					opp-hz = /bits/ 64 <400000000>;
			cpu = <&CPU2>;

			status = "disabled";

			out-ports {
				port {
					etm2_out: endpoint {
						remote-endpoint = <&funnel1_in2>;
					};
				};
				opp-19200000 {
					opp-hz = /bits/ 64 <19200000>;
			};
		};

		etm3: etm@85f000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x0085f000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
			arm,coresight-loses-context-with-cpu;

			cpu = <&CPU3>;

			status = "disabled";

			out-ports {
				port {
					etm3_out: endpoint {
						remote-endpoint = <&funnel1_in3>;
					};
				};
			};
		};

		msmgpio: pinctrl@1000000 {
			compatible = "qcom,msm8916-pinctrl";
			reg = <0x01000000 0x300000>;
			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
			gpio-controller;
			gpio-ranges = <&msmgpio 0 0 122>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gcc: clock-controller@1800000 {
			compatible = "qcom,gcc-msm8916";
			#clock-cells = <1>;
			#reset-cells = <1>;
			#power-domain-cells = <1>;
			reg = <0x01800000 0x80000>;
		};

		tcsr_mutex: hwlock@1905000 {
			compatible = "qcom,tcsr-mutex";
			reg = <0x01905000 0x20000>;
			#hwlock-cells = <1>;
		};

		tcsr: syscon@1937000 {
			compatible = "qcom,tcsr-msm8916", "syscon";
			reg = <0x01937000 0x30000>;
		};

		mdss: mdss@1a00000 {
			compatible = "qcom,mdss";
			reg = <0x01a00000 0x1000>,
@@ -1161,42 +1006,284 @@ dsi_phy0: dsi-phy@1a98300 {
			};
		};

		mpss: remoteproc@4080000 {
			compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
			reg = <0x04080000 0x100>,
			      <0x04020000 0x040>;

			reg-names = "qdsp6", "rmb";

			interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
					      <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";

			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
				 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
				 <&xo_board>;
			clock-names = "iface", "bus", "mem", "xo";

			qcom,smem-states = <&hexagon_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			resets = <&scm 0>;
			reset-names = "mss_restart";

			qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;

		camss: camss@1b00000 {
			compatible = "qcom,msm8916-camss";
			reg = <0x01b0ac00 0x200>,
				<0x01b00030 0x4>,
				<0x01b0b000 0x200>,
				<0x01b00038 0x4>,
				<0x01b08000 0x100>,
				<0x01b08400 0x100>,
				<0x01b0a000 0x500>,
				<0x01b00020 0x10>,
				<0x01b10000 0x1000>;
			reg-names = "csiphy0",
				"csiphy0_clk_mux",
				"csiphy1",
				"csiphy1_clk_mux",
				"csid0",
				"csid1",
				"ispif",
				"csi_clk_mux",
				"vfe0";
			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "csiphy0",
				"csiphy1",
				"csid0",
				"csid1",
				"ispif",
				"vfe0";
			power-domains = <&gcc VFE_GDSC>;
			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
				<&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
				<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
				<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
				<&gcc GCC_CAMSS_CSI0_AHB_CLK>,
				<&gcc GCC_CAMSS_CSI0_CLK>,
				<&gcc GCC_CAMSS_CSI0PHY_CLK>,
				<&gcc GCC_CAMSS_CSI0PIX_CLK>,
				<&gcc GCC_CAMSS_CSI0RDI_CLK>,
				<&gcc GCC_CAMSS_CSI1_AHB_CLK>,
				<&gcc GCC_CAMSS_CSI1_CLK>,
				<&gcc GCC_CAMSS_CSI1PHY_CLK>,
				<&gcc GCC_CAMSS_CSI1PIX_CLK>,
				<&gcc GCC_CAMSS_CSI1RDI_CLK>,
				<&gcc GCC_CAMSS_AHB_CLK>,
				<&gcc GCC_CAMSS_VFE0_CLK>,
				<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
				<&gcc GCC_CAMSS_VFE_AHB_CLK>,
				<&gcc GCC_CAMSS_VFE_AXI_CLK>;
			clock-names = "top_ahb",
				"ispif_ahb",
				"csiphy0_timer",
				"csiphy1_timer",
				"csi0_ahb",
				"csi0",
				"csi0_phy",
				"csi0_pix",
				"csi0_rdi",
				"csi1_ahb",
				"csi1",
				"csi1_phy",
				"csi1_pix",
				"csi1_rdi",
				"ahb",
				"vfe0",
				"csi_vfe0",
				"vfe_ahb",
				"vfe_axi";
			iommus = <&apps_iommu 3>;
			status = "disabled";

			mba {
				memory-region = <&mba_mem>;
			ports {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

			mpss {
		cci: cci@1b0c000 {
			compatible = "qcom,msm8916-cci";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x01b0c000 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
				<&gcc GCC_CAMSS_CCI_AHB_CLK>,
				<&gcc GCC_CAMSS_CCI_CLK>,
				<&gcc GCC_CAMSS_AHB_CLK>;
			clock-names = "camss_top_ahb", "cci_ahb",
					  "cci", "camss_ahb";
			assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
					  <&gcc GCC_CAMSS_CCI_CLK>;
			assigned-clock-rates = <80000000>, <19200000>;
			pinctrl-names = "default";
			pinctrl-0 = <&cci0_default>;
			status = "disabled";

			cci_i2c0: i2c-bus@0 {
				reg = <0>;
				clock-frequency = <400000>;
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};

		gpu@1c00000 {
			compatible = "qcom,adreno-306.0", "qcom,adreno";
			reg = <0x01c00000 0x20000>;
			reg-names = "kgsl_3d0_reg_memory";
			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "kgsl_3d0_irq";
			clock-names =
			    "core",
			    "iface",
			    "mem",
			    "mem_iface",
			    "alt_mem_iface",
			    "gfx3d";
			clocks =
			    <&gcc GCC_OXILI_GFX3D_CLK>,
			    <&gcc GCC_OXILI_AHB_CLK>,
			    <&gcc GCC_OXILI_GMEM_CLK>,
			    <&gcc GCC_BIMC_GFX_CLK>,
			    <&gcc GCC_BIMC_GPU_CLK>,
			    <&gcc GFX3D_CLK_SRC>;
			power-domains = <&gcc OXILI_GDSC>;
			operating-points-v2 = <&gpu_opp_table>;
			iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;

			gpu_opp_table: opp-table {
				compatible = "operating-points-v2";

				opp-400000000 {
					opp-hz = /bits/ 64 <400000000>;
				};
				opp-19200000 {
					opp-hz = /bits/ 64 <19200000>;
				};
			};
		};

		venus: video-codec@1d00000 {
			compatible = "qcom,msm8916-venus";
			reg = <0x01d00000 0xff000>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&gcc VENUS_GDSC>;
			clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
				 <&gcc GCC_VENUS0_AHB_CLK>,
				 <&gcc GCC_VENUS0_AXI_CLK>;
			clock-names = "core", "iface", "bus";
			iommus = <&apps_iommu 5>;
			memory-region = <&venus_mem>;
			status = "okay";

			video-decoder {
				compatible = "venus-decoder";
			};

			video-encoder {
				compatible = "venus-encoder";
			};
		};

		apps_iommu: iommu@1ef0000 {
			#address-cells = <1>;
			#size-cells = <1>;
			#iommu-cells = <1>;
			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
			ranges = <0 0x01e20000 0x40000>;
			reg = <0x01ef0000 0x3000>;
			clocks = <&gcc GCC_SMMU_CFG_CLK>,
				 <&gcc GCC_APSS_TCU_CLK>;
			clock-names = "iface", "bus";
			qcom,iommu-secure-id = <17>;

			// vfe:
			iommu-ctx@3000 {
				compatible = "qcom,msm-iommu-v1-sec";
				reg = <0x3000 0x1000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			};

			// mdp_0:
			iommu-ctx@4000 {
				compatible = "qcom,msm-iommu-v1-ns";
				reg = <0x4000 0x1000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			};

			// venus_ns:
			iommu-ctx@5000 {
				compatible = "qcom,msm-iommu-v1-sec";
				reg = <0x5000 0x1000>;
				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		gpu_iommu: iommu@1f08000 {
			#address-cells = <1>;
			#size-cells = <1>;
			#iommu-cells = <1>;
			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
			ranges = <0 0x01f08000 0x10000>;
			clocks = <&gcc GCC_SMMU_CFG_CLK>,
				 <&gcc GCC_GFX_TCU_CLK>;
			clock-names = "iface", "bus";
			qcom,iommu-secure-id = <18>;

			// gfx3d_user:
			iommu-ctx@1000 {
				compatible = "qcom,msm-iommu-v1-ns";
				reg = <0x1000 0x1000>;
				interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
			};

			// gfx3d_priv:
			iommu-ctx@2000 {
				compatible = "qcom,msm-iommu-v1-ns";
				reg = <0x2000 0x1000>;
				interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		spmi_bus: spmi@200f000 {
			compatible = "qcom,spmi-pmic-arb";
			reg = <0x0200f000 0x001000>,
			      <0x02400000 0x400000>,
			      <0x02c00000 0x400000>,
			      <0x03800000 0x200000>,
			      <0x0200a000 0x002100>;
			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
			interrupt-names = "periph_irq";
			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};

		mpss: remoteproc@4080000 {
			compatible = "qcom,msm8916-mss-pil", "qcom,q6v5-pil";
			reg = <0x04080000 0x100>,
			      <0x04020000 0x040>;

			reg-names = "qdsp6", "rmb";

			interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
					      <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready",
					  "handover", "stop-ack";

			clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
				 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
				 <&gcc GCC_BOOT_ROM_AHB_CLK>,
				 <&xo_board>;
			clock-names = "iface", "bus", "mem", "xo";

			qcom,smem-states = <&hexagon_smp2p_out 0>;
			qcom,smem-state-names = "stop";

			resets = <&scm 0>;
			reset-names = "mss_restart";

			qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>;

			status = "disabled";

			mba {
				memory-region = <&mba_mem>;
			};

			mpss {
				memory-region = <&mpss_mem>;
			};

@@ -1225,690 +1312,603 @@ cb@1 {
			};
		};

		pronto: remoteproc@a21b000 {
			compatible = "qcom,pronto-v2-pil", "qcom,pronto";
			reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
			reg-names = "ccu", "dxe", "pmu";

			memory-region = <&wcnss_mem>;

			interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";

			qcom,state = <&wcnss_smp2p_out 0>;
			qcom,state-names = "stop";

			pinctrl-names = "default";
			pinctrl-0 = <&wcnss_pin_a>;
		sound: sound@7702000 {
			status = "disabled";
			compatible = "qcom,apq8016-sbc-sndcard";
			reg = <0x07702000 0x4>, <0x07702004 0x4>;
			reg-names = "mic-iomux", "spkr-iomux";
		};

		lpass: audio-controller@7708000 {
			status = "disabled";
			compatible = "qcom,lpass-cpu-apq8016";
			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
				 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
				 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
				 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>;

			iris {
				compatible = "qcom,wcn3620";
			clock-names = "ahbix-clk",
					"pcnoc-mport-clk",
					"pcnoc-sway-clk",
					"mi2s-bit-clk0",
					"mi2s-bit-clk1",
					"mi2s-bit-clk2",
					"mi2s-bit-clk3";
			#sound-dai-cells = <1>;

				clocks = <&rpmcc RPM_SMD_RF_CLK2>;
				clock-names = "xo";
			};
			interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "lpass-irq-lpaif";
			reg = <0x07708000 0x10000>;
			reg-names = "lpass-lpaif";

			smd-edge {
				interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
			#address-cells = <1>;
			#size-cells = <0>;
		};

				qcom,ipc = <&apcs 8 17>;
				qcom,smd-edge = <6>;
				qcom,remote-pid = <4>;

				label = "pronto";

				wcnss {
					compatible = "qcom,wcnss";
					qcom,smd-channels = "WCNSS_CTRL";

					qcom,mmio = <&pronto>;

					bt {
						compatible = "qcom,wcnss-bt";
					};

					wifi {
						compatible = "qcom,wcnss-wlan";

						interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
							     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
						interrupt-names = "tx", "rx";

						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
						qcom,smem-state-names = "tx-enable", "tx-rings-empty";
					};
				};
			};
		};

		tpiu: tpiu@820000 {
			compatible = "arm,coresight-tpiu", "arm,primecell";
			reg = <0x00820000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			status = "disabled";

			in-ports {
				port {
					tpiu_in: endpoint {
						remote-endpoint = <&replicator_out1>;
					};
				};
			};
		};

		funnel0: funnel@821000 {
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x00821000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

			status = "disabled";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				/*
				 * Not described input ports:
				 * 0 - connected to Resource and Power Manger CPU ETM
				 * 1 - not-connected
				 * 2 - connected to Modem CPU ETM
				 * 3 - not-connected
				 * 5 - not-connected
				 * 6 - connected trought funnel to Wireless CPU ETM
				 * 7 - connected to STM component
				 */

				port@4 {
					reg = <4>;
					funnel0_in4: endpoint {
						remote-endpoint = <&funnel1_out>;
					};
				};
			};

			out-ports {
				port {
					funnel0_out: endpoint {
						remote-endpoint = <&etf_in>;
					};
				};
			};
		lpass_codec: audio-codec@771c000 {
			compatible = "qcom,msm8916-wcd-digital-codec";
			reg = <0x0771c000 0x400>;
			clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
				 <&gcc GCC_CODEC_DIGCODEC_CLK>;
			clock-names = "ahbix-clk", "mclk";
			#sound-dai-cells = <1>;
		};

		replicator: replicator@824000 {
			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
			reg = <0x00824000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
		sdhc_1: sdhci@7824000 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x07824900 0x11c>, <0x07824000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>,
				 <&gcc GCC_SDCC1_AHB_CLK>,
				 <&xo_board>;
			clock-names = "core", "iface", "xo";
			mmc-ddr-1_8v;
			bus-width = <8>;
			non-removable;
			status = "disabled";

			out-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					replicator_out0: endpoint {
						remote-endpoint = <&etr_in>;
					};
				};
				port@1 {
					reg = <1>;
					replicator_out1: endpoint {
						remote-endpoint = <&tpiu_in>;
					};
				};
			};

			in-ports {
				port {
					replicator_in: endpoint {
						remote-endpoint = <&etf_out>;
					};
				};
			};
		};

		etf: etf@825000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x00825000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
		sdhc_2: sdhci@7864000 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0x07864900 0x11c>, <0x07864000 0x800>;
			reg-names = "hc_mem", "core_mem";

			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>,
				 <&gcc GCC_SDCC2_AHB_CLK>,
				 <&xo_board>;
			clock-names = "core", "iface", "xo";
			bus-width = <4>;
			status = "disabled";

			in-ports {
				port {
					etf_in: endpoint {
						remote-endpoint = <&funnel0_out>;
					};
				};
			};

			out-ports {
				port {
					etf_out: endpoint {
						remote-endpoint = <&replicator_in>;
					};
				};
			};
		};

		etr: etr@826000 {
			compatible = "arm,coresight-tmc", "arm,primecell";
			reg = <0x00826000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

		blsp_dma: dma@7884000 {
			compatible = "qcom,bam-v1.7.0";
			reg = <0x07884000 0x23000>;
			interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "bam_clk";
			#dma-cells = <1>;
			qcom,ee = <0>;
			status = "disabled";

			in-ports {
				port {
					etr_in: endpoint {
						remote-endpoint = <&replicator_out0>;
					};
				};
			};
		};

		funnel1: funnel@841000 {	/* APSS funnel only 4 inputs are used */
			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
			reg = <0x00841000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";

		blsp1_uart1: serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078af000 0x200>;
			interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 1>, <&blsp_dma 0>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_uart1_default>;
			pinctrl-1 = <&blsp1_uart1_sleep>;
			status = "disabled";

			in-ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					funnel1_in0: endpoint {
						remote-endpoint = <&etm0_out>;
					};
				};
				port@1 {
					reg = <1>;
					funnel1_in1: endpoint {
						remote-endpoint = <&etm1_out>;
					};
				};
				port@2 {
					reg = <2>;
					funnel1_in2: endpoint {
						remote-endpoint = <&etm2_out>;
					};
				};
				port@3 {
					reg = <3>;
					funnel1_in3: endpoint {
						remote-endpoint = <&etm3_out>;
					};
				};
			};

			out-ports {
				port {
					funnel1_out: endpoint {
						remote-endpoint = <&funnel0_in4>;
					};
				};
			};
		};

		debug0: debug@850000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x00850000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU0>;
		blsp1_uart2: serial@78b0000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x078b0000 0x200>;
			interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 3>, <&blsp_dma 2>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&blsp1_uart2_default>;
			pinctrl-1 = <&blsp1_uart2_sleep>;
			status = "disabled";
		};

		debug1: debug@852000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x00852000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU1>;
		blsp_i2c1: i2c@78b5000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b5000 0x500>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c1_default>;
			pinctrl-1 = <&i2c1_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		debug2: debug@854000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x00854000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU2>;
		blsp_spi1: spi@78b5000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b5000 0x500>;
			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 5>, <&blsp_dma 4>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi1_default>;
			pinctrl-1 = <&spi1_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		debug3: debug@856000 {
			compatible = "arm,coresight-cpu-debug", "arm,primecell";
			reg = <0x00856000 0x1000>;
			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			cpu = <&CPU3>;
		blsp_i2c2: i2c@78b6000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b6000 0x500>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c2_default>;
			pinctrl-1 = <&i2c2_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		etm0: etm@85c000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x0085c000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
			arm,coresight-loses-context-with-cpu;

			cpu = <&CPU0>;

		blsp_spi2: spi@78b6000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b6000 0x500>;
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 7>, <&blsp_dma 6>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi2_default>;
			pinctrl-1 = <&spi2_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			out-ports {
				port {
					etm0_out: endpoint {
						remote-endpoint = <&funnel1_in0>;
					};
				};
			};
		};

		etm1: etm@85d000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x0085d000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
			arm,coresight-loses-context-with-cpu;

			cpu = <&CPU1>;

		blsp_spi3: spi@78b7000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b7000 0x500>;
			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 9>, <&blsp_dma 8>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi3_default>;
			pinctrl-1 = <&spi3_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			out-ports {
				port {
					etm1_out: endpoint {
						remote-endpoint = <&funnel1_in1>;
					};
				};
			};
		};

		etm2: etm@85e000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x0085e000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
			arm,coresight-loses-context-with-cpu;

			cpu = <&CPU2>;

		blsp_i2c4: i2c@78b8000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b8000 0x500>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c4_default>;
			pinctrl-1 = <&i2c4_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			out-ports {
				port {
					etm2_out: endpoint {
						remote-endpoint = <&funnel1_in2>;
					};
				};
			};
		};

		etm3: etm@85f000 {
			compatible = "arm,coresight-etm4x", "arm,primecell";
			reg = <0x0085f000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
			clock-names = "apb_pclk", "atclk";
			arm,coresight-loses-context-with-cpu;

			cpu = <&CPU3>;

		blsp_spi4: spi@78b8000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b8000 0x500>;
			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 11>, <&blsp_dma 10>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi4_default>;
			pinctrl-1 = <&spi4_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			out-ports {
				port {
					etm3_out: endpoint {
						remote-endpoint = <&funnel1_in3>;
					};
				};
			};
		};

		/* System CTIs */
		/* CTI 0 - TMC connections */
		cti0: cti@810000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x00810000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

		blsp_i2c5: i2c@78b9000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078b9000 0x500>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c5_default>;
			pinctrl-1 = <&i2c5_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		/* CTI 1 - TPIU connections */
		cti1: cti@811000 {
			compatible = "arm,coresight-cti", "arm,primecell";
			reg = <0x00811000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

		blsp_spi5: spi@78b9000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078b9000 0x500>;
			interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 13>, <&blsp_dma 12>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi5_default>;
			pinctrl-1 = <&spi5_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		/* CTIs 2-11 - no information - not instantiated */

		/* Core CTIs; CTIs 12-15 */
		/* CTI - CPU-0 */
		cti12: cti@858000 {
			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
				     "arm,primecell";
			reg = <0x00858000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

			cpu = <&CPU0>;
			arm,cs-dev-assoc = <&etm0>;

		blsp_i2c6: i2c@78ba000 {
			compatible = "qcom,i2c-qup-v2.2.1";
			reg = <0x078ba000 0x500>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_AHB_CLK>,
				 <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
			clock-names = "iface", "core";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&i2c6_default>;
			pinctrl-1 = <&i2c6_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		/* CTI - CPU-1 */
		cti13: cti@859000 {
			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
				     "arm,primecell";
			reg = <0x00859000 0x1000>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";

			cpu = <&CPU1>;
			arm,cs-dev-assoc = <&etm1>;

		blsp_spi6: spi@78ba000 {
			compatible = "qcom,spi-qup-v2.2.1";
			reg = <0x078ba000 0x500>;
			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
				 <&gcc GCC_BLSP1_AHB_CLK>;
			clock-names = "core", "iface";
			dmas = <&blsp_dma 15>, <&blsp_dma 14>;
			dma-names = "rx", "tx";
			pinctrl-names = "default", "sleep";
			pinctrl-0 = <&spi6_default>;
			pinctrl-1 = <&spi6_sleep>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		/* CTI - CPU-2 */
		cti14: cti@85a000 {
			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
				     "arm,primecell";
			reg = <0x0085a000 0x1000>;
		usb: usb@78d9000 {
			compatible = "qcom,ci-hdrc";
			reg = <0x078d9000 0x200>,
			      <0x078d9200 0x200>;
			interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&gcc GCC_USB_HS_AHB_CLK>,
				 <&gcc GCC_USB_HS_SYSTEM_CLK>;
			clock-names = "iface", "core";
			assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
			assigned-clock-rates = <80000000>;
			resets = <&gcc GCC_USB_HS_BCR>;
			reset-names = "core";
			phy_type = "ulpi";
			dr_mode = "otg";
			hnp-disable;
			srp-disable;
			adp-disable;
			ahb-burst-config = <0>;
			phy-names = "usb-phy";
			phys = <&usb_hs_phy>;
			status = "disabled";
			#reset-cells = <1>;

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			ulpi {
				usb_hs_phy: phy {
					compatible = "qcom,usb-hs-phy-msm8916",
						     "qcom,usb-hs-phy";
					#phy-cells = <0>;
					clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
					clock-names = "ref", "sleep";
					resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
					reset-names = "phy", "por";
					qcom,init-seq = /bits/ 8 <0x0 0x44
						0x1 0x6b 0x2 0x24 0x3 0x13>;
				};
			};
		};

			cpu = <&CPU2>;
			arm,cs-dev-assoc = <&etm2>;
		pronto: remoteproc@a21b000 {
			compatible = "qcom,pronto-v2-pil", "qcom,pronto";
			reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
			reg-names = "ccu", "dxe", "pmu";

			status = "disabled";
		};
			memory-region = <&wcnss_mem>;

		/* CTI - CPU-3 */
		cti15: cti@85b000 {
			compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti",
				     "arm,primecell";
			reg = <0x0085b000 0x1000>;
			interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
					      <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";

			clocks = <&rpmcc RPM_QDSS_CLK>;
			clock-names = "apb_pclk";
			qcom,state = <&wcnss_smp2p_out 0>;
			qcom,state-names = "stop";

			cpu = <&CPU3>;
			arm,cs-dev-assoc = <&etm3>;
			pinctrl-names = "default";
			pinctrl-0 = <&wcnss_pin_a>;

			status = "disabled";
		};

		venus: video-codec@1d00000 {
			compatible = "qcom,msm8916-venus";
			reg = <0x01d00000 0xff000>;
			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
			power-domains = <&gcc VENUS_GDSC>;
			clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
				 <&gcc GCC_VENUS0_AHB_CLK>,
				 <&gcc GCC_VENUS0_AXI_CLK>;
			clock-names = "core", "iface", "bus";
			iommus = <&apps_iommu 5>;
			memory-region = <&venus_mem>;
			status = "okay";
			iris {
				compatible = "qcom,wcn3620";

			video-decoder {
				compatible = "venus-decoder";
				clocks = <&rpmcc RPM_SMD_RF_CLK2>;
				clock-names = "xo";
			};

			video-encoder {
				compatible = "venus-encoder";
			};
		};
			smd-edge {
				interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;

		camss: camss@1b00000 {
			compatible = "qcom,msm8916-camss";
			reg = <0x01b0ac00 0x200>,
				<0x01b00030 0x4>,
				<0x01b0b000 0x200>,
				<0x01b00038 0x4>,
				<0x01b08000 0x100>,
				<0x01b08400 0x100>,
				<0x01b0a000 0x500>,
				<0x01b00020 0x10>,
				<0x01b10000 0x1000>;
			reg-names = "csiphy0",
				"csiphy0_clk_mux",
				"csiphy1",
				"csiphy1_clk_mux",
				"csid0",
				"csid1",
				"ispif",
				"csi_clk_mux",
				"vfe0";
			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
				<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "csiphy0",
				"csiphy1",
				"csid0",
				"csid1",
				"ispif",
				"vfe0";
			power-domains = <&gcc VFE_GDSC>;
			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
				<&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
				<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
				<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
				<&gcc GCC_CAMSS_CSI0_AHB_CLK>,
				<&gcc GCC_CAMSS_CSI0_CLK>,
				<&gcc GCC_CAMSS_CSI0PHY_CLK>,
				<&gcc GCC_CAMSS_CSI0PIX_CLK>,
				<&gcc GCC_CAMSS_CSI0RDI_CLK>,
				<&gcc GCC_CAMSS_CSI1_AHB_CLK>,
				<&gcc GCC_CAMSS_CSI1_CLK>,
				<&gcc GCC_CAMSS_CSI1PHY_CLK>,
				<&gcc GCC_CAMSS_CSI1PIX_CLK>,
				<&gcc GCC_CAMSS_CSI1RDI_CLK>,
				<&gcc GCC_CAMSS_AHB_CLK>,
				<&gcc GCC_CAMSS_VFE0_CLK>,
				<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
				<&gcc GCC_CAMSS_VFE_AHB_CLK>,
				<&gcc GCC_CAMSS_VFE_AXI_CLK>;
			clock-names = "top_ahb",
				"ispif_ahb",
				"csiphy0_timer",
				"csiphy1_timer",
				"csi0_ahb",
				"csi0",
				"csi0_phy",
				"csi0_pix",
				"csi0_rdi",
				"csi1_ahb",
				"csi1",
				"csi1_phy",
				"csi1_pix",
				"csi1_rdi",
				"ahb",
				"vfe0",
				"csi_vfe0",
				"vfe_ahb",
				"vfe_axi";
			iommus = <&apps_iommu 3>;
			status = "disabled";
			ports {
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};
				qcom,ipc = <&apcs 8 17>;
				qcom,smd-edge = <6>;
				qcom,remote-pid = <4>;

		cci: cci@1b0c000 {
			compatible = "qcom,msm8916-cci";
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x01b0c000 0x1000>;
			interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
				<&gcc GCC_CAMSS_CCI_AHB_CLK>,
				<&gcc GCC_CAMSS_CCI_CLK>,
				<&gcc GCC_CAMSS_AHB_CLK>;
			clock-names = "camss_top_ahb", "cci_ahb",
					  "cci", "camss_ahb";
			assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
					  <&gcc GCC_CAMSS_CCI_CLK>;
			assigned-clock-rates = <80000000>, <19200000>;
			pinctrl-names = "default";
			pinctrl-0 = <&cci0_default>;
			status = "disabled";
				label = "pronto";

				wcnss {
					compatible = "qcom,wcnss";
					qcom,smd-channels = "WCNSS_CTRL";

			cci_i2c0: i2c-bus@0 {
				reg = <0>;
				clock-frequency = <400000>;
				#address-cells = <1>;
				#size-cells = <0>;
			};
		};
	};
					qcom,mmio = <&pronto>;

	smd {
		compatible = "qcom,smd";
					bt {
						compatible = "qcom,wcnss-bt";
					};

		rpm {
			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
			qcom,ipc = <&apcs 8 0>;
			qcom,smd-edge = <15>;
					wifi {
						compatible = "qcom,wcnss-wlan";

			rpm_requests: rpm-requests {
				compatible = "qcom,rpm-msm8916";
				qcom,smd-channels = "rpm_requests";
						interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
							     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
						interrupt-names = "tx", "rx";

				rpmcc: clock-controller {
					compatible = "qcom,rpmcc-msm8916";
					#clock-cells = <1>;
						qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
						qcom,smem-state-names = "tx-enable", "tx-rings-empty";
					};
				};
			};
		};
	};

	smp2p-hexagon {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		intc: interrupt-controller@b000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
		};

		interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
		apcs: mailbox@b011000 {
			compatible = "qcom,msm8916-apcs-kpss-global", "syscon";
			reg = <0x0b011000 0x1000>;
			#mbox-cells = <1>;
			clocks = <&a53pll>, <&gcc GPLL0_VOTE>;
			clock-names = "pll", "aux";
			#clock-cells = <0>;
		};

		qcom,ipc = <&apcs 8 14>;
		a53pll: clock@b016000 {
			compatible = "qcom,msm8916-a53pll";
			reg = <0x0b016000 0x40>;
			#clock-cells = <0>;
		};

		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;
		timer@b020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0x0b020000 0x1000>;
			clock-frequency = <19200000>;

		hexagon_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			frame@b021000 {
				frame-number = <0>;
				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b021000 0x1000>,
				      <0x0b022000 0x1000>;
			};

			#qcom,smem-state-cells = <1>;
		};
			frame@b023000 {
				frame-number = <1>;
				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b023000 0x1000>;
				status = "disabled";
			};

		hexagon_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			frame@b024000 {
				frame-number = <2>;
				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b024000 0x1000>;
				status = "disabled";
			};

			interrupt-controller;
			#interrupt-cells = <2>;
			frame@b025000 {
				frame-number = <3>;
				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b025000 0x1000>;
				status = "disabled";
			};

			frame@b026000 {
				frame-number = <4>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b026000 0x1000>;
				status = "disabled";
			};

			frame@b027000 {
				frame-number = <5>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b027000 0x1000>;
				status = "disabled";
			};

			frame@b028000 {
				frame-number = <6>;
				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
				reg = <0x0b028000 0x1000>;
				status = "disabled";
			};
		};
	};

	smp2p-wcnss {
		compatible = "qcom,smp2p";
		qcom,smem = <451>, <431>;
	thermal-zones {
		cpu0-1-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

		interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
			thermal-sensors = <&tsens 5>;

		qcom,ipc = <&apcs 8 18>;
			trips {
				cpu0_1_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu0_1_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

		qcom,local-pid = <0>;
		qcom,remote-pid = <4>;
			cooling-maps {
				map0 {
					trip = <&cpu0_1_alert0>;
					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};

		wcnss_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
		cpu2-3-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			#qcom,smem-state-cells = <1>;
		};
			thermal-sensors = <&tsens 4>;

		wcnss_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			trips {
				cpu2_3_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				cpu2_3_crit: cpu_crit {
					temperature = <110000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};

			interrupt-controller;
			#interrupt-cells = <2>;
			cooling-maps {
				map0 {
					trip = <&cpu2_3_alert0>;
					cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
							 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
				};
			};
		};
	};

	smsm {
		compatible = "qcom,smsm";
		gpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

		#address-cells = <1>;
		#size-cells = <0>;
			thermal-sensors = <&tsens 2>;

		qcom,ipc-1 = <&apcs 8 13>;
		qcom,ipc-3 = <&apcs 8 19>;
			trips {
				gpu_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "passive";
				};
				gpu_crit: gpu_crit {
					temperature = <95000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};

		apps_smsm: apps@0 {
			reg = <0>;
		camera-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			#qcom,smem-state-cells = <1>;
			thermal-sensors = <&tsens 1>;

			trips {
				cam_alert0: trip-point0 {
					temperature = <75000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		hexagon_smsm: hexagon@1 {
			reg = <1>;
			interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
		modem-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;

			interrupt-controller;
			#interrupt-cells = <2>;
			thermal-sensors = <&tsens 0>;

			trips {
				modem_alert0: trip-point0 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "hot";
				};
			};
		};

		wcnss_smsm: wcnss@6 {
			reg = <6>;
			interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
	};

			interrupt-controller;
			#interrupt-cells = <2>;
		};
	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};
};

-- 
2.28.0

[PATCH 13/14] arm64: dts: qcom: pm8916: Sort nodes Export this patch

Stephan Gerhold
Sort nodes by unit address so we have a consistent order in pm8916.dtsi.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
 arch/arm64/boot/dts/qcom/pm8916.dtsi | 60 ++++++++++++++--------------
 1 file changed, 30 insertions(+), 30 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi
index c7b22ac81452..f931cb0de231 100644
--- a/arch/arm64/boot/dts/qcom/pm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/spmi/spmi.h>

&spmi_bus {
@@ -12,13 +12,6 @@ pm8916_0: pmic@0 {
		#address-cells = <1>;
		#size-cells = <0>;

		rtc@6000 {
			compatible = "qcom,pm8941-rtc";
			reg = <0x6000>;
			reg-names = "rtc", "alarm";
			interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
		};

		pon@800 {
			compatible = "qcom,pm8916-pon";
			reg = <0x800>;
@@ -48,28 +41,6 @@ watchdog {
			};
		};

		pm8916_gpios: gpios@c000 {
			compatible = "qcom,pm8916-gpio";
			reg = <0xc000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
				     <0 0xc1 0 IRQ_TYPE_NONE>,
				     <0 0xc2 0 IRQ_TYPE_NONE>,
				     <0 0xc3 0 IRQ_TYPE_NONE>;
		};

		pm8916_mpps: mpps@a000 {
			compatible = "qcom,pm8916-mpp";
			reg = <0xa000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
				     <0 0xa1 0 IRQ_TYPE_NONE>,
				     <0 0xa2 0 IRQ_TYPE_NONE>,
				     <0 0xa3 0 IRQ_TYPE_NONE>;
		};

		pm8916_temp: temp-alarm@2400 {
			compatible = "qcom,spmi-temp-alarm";
			reg = <0x2400>;
@@ -111,6 +82,35 @@ adc-chan@f {
				reg = <VADC_VDD_VADC>;
			};
		};

		rtc@6000 {
			compatible = "qcom,pm8941-rtc";
			reg = <0x6000>;
			reg-names = "rtc", "alarm";
			interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
		};

		pm8916_mpps: mpps@a000 {
			compatible = "qcom,pm8916-mpp";
			reg = <0xa000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <0 0xa0 0 IRQ_TYPE_NONE>,
				     <0 0xa1 0 IRQ_TYPE_NONE>,
				     <0 0xa2 0 IRQ_TYPE_NONE>,
				     <0 0xa3 0 IRQ_TYPE_NONE>;
		};

		pm8916_gpios: gpios@c000 {
			compatible = "qcom,pm8916-gpio";
			reg = <0xc000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <0 0xc0 0 IRQ_TYPE_NONE>,
				     <0 0xc1 0 IRQ_TYPE_NONE>,
				     <0 0xc2 0 IRQ_TYPE_NONE>,
				     <0 0xc3 0 IRQ_TYPE_NONE>;
		};
	};

	pm8916_1: pmic@1 {
-- 
2.28.0

[PATCH 14/14] arm64: dts: qcom: Makefile: Sort lines Export this patch

Stephan Gerhold
The Makefile is in a bit of a weird order at the moment.
It's almost sorted alphabetically, but not entirely.
Also, one element uses a space before the += instead of a tab.

Fix this up and sort the lines alphabetically so we have
a consistent order in the Makefile.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
---
 arch/arm64/boot/dts/qcom/Makefile | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 7d71a51ca4ea..fb4631f898fd 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -1,11 +1,11 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_QCOM)	+= apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= ipq6018-cp01-c1.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-longcheer-l8150.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-a3u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= msm8916-samsung-a5u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= msm8992-bullhead-rev-101.dtb
@@ -18,6 +18,9 @@ dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-asus-novago-tp370ql.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-hp-envy-x2.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-lenovo-miix-630.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= msm8998-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= qrb5165-rb5.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-idp.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-r0.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= sc7180-trogdor-lazor-r1.dtb
@@ -40,6 +43,3 @@ dtb-$(CONFIG_ARCH_QCOM)	+= sdm845-xiaomi-beryllium.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= sdm850-lenovo-yoga-c630.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= sm8150-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= sm8250-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= qcs404-evb-4000.dtb
dtb-$(CONFIG_ARCH_QCOM)	+= qrb5165-rb5.dtb
-- 
2.28.0