Hi,
Apple's A10(X), T2 SoCs consists of pairs of performance and efficiency
cores. However, only one of the core types may be active at a given time,
and to software, it appears as logical cores that could switch between
P-mode and E-mode, depending on the p-state.
Unforunately, only the performance cores can execute 32-bit EL0. To
software, this results in logical cores that lose ability to execute
32-bit EL0 when the p-state is below a certain value.
Since these CPU cores only supported 16K pages, many AArch32
executables will not run anyways. This series disables 32-bit EL0 for
these SoCs.
Nick Chan
---
Nick Chan (2):
arm64: cputype: Add CPU types for A7-A11, T2 SoCs
arm64: cpufeature: Pretend that Apple A10(X), T2 does not support
32-bit EL0
arch/arm64/include/asm/cputype.h | 42 +++++++++++++++++++++++---------
arch/arm64/kernel/cpufeature.c | 25 +++++++++++++++++++
2 files changed, 55 insertions(+), 12 deletions(-)
base-commit: 9aaeb87ce1e966169a57f53a02ba05b30880ffb8
--
2.46.0
The Apple A10(X), T2 consists of logical cores that can switch
between P-mode and E-mode based on the frequency. However, only
P-mode supported 32-bit EL0.
Trying to support 32-bit EL0 on a CPU that can only execute it in certain
states is a bad idea. The A10(X), T2 only supports 16KB page size anyway so
many AArch32 executables won't run anyways. Pretend that it does not
support 32-bit EL0 at all.
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
---
arch/arm64/kernel/cpufeature.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 718728a85430..458bcbc4f328 100644
--- a/arch/arm64/kernel/cpufeature.c+++ b/arch/arm64/kernel/cpufeature.c
@@ -3529,6 +3529,29 @@ void __init setup_boot_cpu_features(void)
setup_boot_cpu_capabilities();
}
+static void __init bad_aarch32_el0_fixup(void)+{+#ifdef CONFIG_ARCH_APPLE+ static const struct midr_range bad_aarch32_el0[] = {+ MIDR_ALL_VERSIONS(MIDR_APPLE_A10_T2_HURRICANE_ZEPHYR),+ MIDR_ALL_VERSIONS(MIDR_APPLE_A10X_HURRICANE_ZEPHYR),+ {}+ };++ if (is_midr_in_range_list(read_cpuid_id(), bad_aarch32_el0)) {+ struct arm64_ftr_reg *regp;++ regp = get_arm64_ftr_reg(SYS_ID_AA64PFR0_EL1);+ if (!regp)+ return;+ u64 val = (regp->sys_val & ~ID_AA64PFR0_EL1_EL0_MASK)+ | ID_AA64PFR0_EL1_EL0_IMP;++ update_cpu_ftr_reg(regp, val);+ }+#endif+}+static void __init setup_system_capabilities(void)
{
/*
@@ -3562,6 +3585,8 @@ static void __init setup_system_capabilities(void)
void __init setup_system_features(void)
{
+ bad_aarch32_el0_fixup();+ setup_system_capabilities();
kpti_install_ng_mappings();
--
2.46.0