Hi! I’m currently a PhD student in the Circuits and Systems group at Imperial College London, supervised by John Wickerson.
My research focuses on formalising the process of converting high-level programming language descriptions to correct hardware that is functionally equivalent to the input. This process is called high-level synthesis (HLS), and allows software to be turned into custom accelerators automatically, which can then be placed on field-programmable gate arrays (FPGAs). An implementation in the Coq theorem prover called Vericert can be found on Github.
I have also worked on random testing for FPGA synthesis tools. Verismith is a fuzzer that will randomly generate a Verilog design, pass it to the synthesis tool, and use an equivalence check to compare the output to the input. If these differ, the design is automatically reduced until the bug is located.
From Yann Herklotz to ~ymherklotz/ymh-emacs
Submitting a first patch by email, containing some simple stylistic changes. --- This patch includes some simplifications for options and tuareg-mode. init.el | 119 ++++++++++++++++++++++++++++++-------------------------- 1 file changed, 64 insertions(+), 55 deletions(-) diff --git a/init.el b/init.el index a2110db..5b21b27 100644 --- a/init.el +++ b/init.el @@ -329,17 +329,17 @@ https://yannherklotz.com")) [message trimmed]
From Yann Herklotz to ~ymherklotz/org-zettelkasten
Announcing the release of version 0.6.2 of Org Zettelkasten. The main change in this release is the separation of Zettelkasten mode and Org Zettelkasten. These were previously in a single repository, however, because they are separate packages, they belong in different repositories. In addition to that, specifically with changes related to Org Zettelkasten since version 0.5: - Add new customisation mapping for base identifiers to files (`org-zettelkasten-mapping`). - Add function to go straight to an ID using only the number (`org-zettelkasten-goto-id`).